AD5737X

更新时间： 2024-02-28 19:46:37

品牌	Logo	应用领域
亚德诺 - ADI		转换器数模转换器功率控制
页数	文件大小	规格书
31页	640K
描述
Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity

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技术参数
数据手册

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AD5737X 技术参数

生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	,	针数：	64
Reach Compliance Code：	unknown	风险等级：	5.77
Is Samacsys：	N	转换器类型：	D/A CONVERTER
JESD-30 代码：	S-XQCC-N64	位数：	16
端子数量：	64	封装主体材料：	UNSPECIFIED
封装形状：	SQUARE	封装形式：	CHIP CARRIER
认证状态：	Not Qualified	表面贴装：	YES
端子形式：	NO LEAD	端子位置：	QUAD
Base Number Matches：	1

AD5737X 数据手册

AD5757/AD5737

Preliminary Technical Data

TIMING CHARACTERISTICS

AVDD = 15V, AVSS = 0V/-15 V, V_BOOSTA,B,C,D= +10.8 V to +33 V, DVDD = AVCC = 2.7 V to 5.5 V, DCDC disabled, AGND = DGND =

GNDSW_A,B,C,D= 0 V, REFIN= +5, V_OUT: R_L= 1kΩ, C_L= 220pF, I_OUT: R_L= 300Ω, all specifications T_MINto T_MAXunless otherwise noted.

Table 4.

Parameter^{1, 2, 3}

Limit at T_MIN, T_MAX

Unit

Description

t₁

t₂

t₃

t₄

ns min

SCLK cycle time

SCLK high time

SCLK low time

falling edge to SCLK falling edge setup time

SYNC

t₅

t₆

ns min

24/32nd SCLK falling edge to

rising edge

SYNC

198

high time

SYNC

t₇

t₈

t₉

ns min

µs min

Data setup time

Data hold time

rising edge to

SYNC

channel has digital slew rate control enabled)

falling edge (all DACs updated or any

LDAC

µs min

ns min

ns max

µs max

rising edge to

falling edge (single DAC updated)

SYNC

LDAC

pulse width low

falling edge to DAC output response time

t₁₀

t₁₁

t₁₂

500

See AC Performance

Characteristics

DAC output settling time

t₁₃

t₁₄

t₁₅

t₁₆

TBD

ns min

µs max

ns max

µs min

CLEAR high time

CLEAR activation time

SCLK rising edge to SDO valid (C_{L SDO}= 35 pF)

rising edge to DAC output response time (LDAC = 0) (all DACs

SYNC

updated)

µs min

rising edge to DAC output response time (LDAC = 0) (single

SYNC

DAC updated)

t₁₇

t₁₈

t₁₉

500

700

ns min

µs min

falling edge to

rising edge

SYNC

LDAC

RESET pulsewidth

high to next

low (Ramp enabled)

low (Ramp disabled)

SYNC

high to next

¹Guaranteed by design and characterization; not production tested.

²All input signals are specified with t_R= t_F= 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.

³See Figure 2 , Figure 3 , Figure 4 and Figure 5

Rev. PrD | Page 6 of 31

1...3 4 567 8 9...31

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