Datasheet > AD5624BRMZ-REEL7

AD5624BRMZ-REEL7

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	631K
描述
2.7 V to 5.5 V, 450 レA, Rail-to-Rail Output, Quad, 12-/16-Bit nanoDACs

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AD5624BRMZ-REEL7 数据手册

AD5624/AD5664

TIMING CHARACTERISTICS

All input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of V_DD) and timed from a voltage level of (V_Iꢀ+ V_IH)/2 (see Figure 2).

_DD= 2.7 V to 5.5 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 4.

Limit at T_MIN, T_MAX

V_DD= 2.7 V to 5.5 V

Parameter¹

Unit

Conditions/Comments

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge setup time

Data setup time

t₁

ns min

t₂

t₃

t₄

t₅

t₆

t₇

t_±

t₉

t₁₀

Data hold time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

SYNC rising edge to SCLK fall ignore

SCLK falling edge to SYNC fall ignore

¹Guaranteed by design and characterization, not production tested.

²Maximum SCLK frequency is 50 MHz at V_DD= 2.7 V to 5.5 V.

TIMING DIAGRAM

t₁₀

t₁

t₉

SCLK

t₂

t₈

t₃

t₇

t₄

SYNC

DIN

t₆

t₅

DB23

DB0

Figure 2. Serial Write Operation

Rev. 0 | Page 5 of 24

1 2 3 456 7 8...24

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