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AD5623RBCPZ-3REEL7 PDF预览

AD5623RBCPZ-3REEL7

更新时间: 2024-02-14 05:27:13
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 1396K
描述
Dual 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference

AD5623RBCPZ-3REEL7 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:HVSON, SOLCC10,.11,20针数:10
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.14
最大模拟输出电压:3.6 V最小模拟输出电压:
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:S-PDSO-N10
JESD-609代码:e3长度:3 mm
最大线性误差 (EL):0.0244%湿度敏感等级:1
位数:12功能数量:1
端子数量:10最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVSON封装等效代码:SOLCC10,.11,20
封装形状:SQUARE封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3/5 V
认证状态:Not Qualified座面最大高度:0.85 mm
最大稳定时间:4.5 µs标称安定时间 (tstl):3 µs
子类别:Other Converters标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3 mmBase Number Matches:1

AD5623RBCPZ-3REEL7 数据手册

 浏览型号AD5623RBCPZ-3REEL7的Datasheet PDF文件第2页浏览型号AD5623RBCPZ-3REEL7的Datasheet PDF文件第3页浏览型号AD5623RBCPZ-3REEL7的Datasheet PDF文件第4页浏览型号AD5623RBCPZ-3REEL7的Datasheet PDF文件第6页浏览型号AD5623RBCPZ-3REEL7的Datasheet PDF文件第7页浏览型号AD5623RBCPZ-3REEL7的Datasheet PDF文件第8页 
AD5623R/AD5643R/AD5663R  
AD5623R-3/AD5643R-3/AD5663R-3  
VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.  
Table 3.  
B Grade1  
Parameter  
STATIC PERFORMANCE2  
Min  
Typ  
Max  
Unit  
Conditions/Comments  
AD5663R  
Resolution  
16  
Bits  
LSB  
LSB  
Relative Accuracy  
Differential Nonlinearity  
AD5643R  
±8  
±16  
±1  
Guaranteed monotonic by design  
Guaranteed monotonic by design  
Resolution  
14  
12  
Bits  
LSB  
LSB  
Relative Accuracy  
Differential Nonlinearity  
AD5623R  
±2  
±4  
±±.5  
Resolution  
Bits  
Relative Accuracy  
Differential Nonlinearity  
Zero-Scale Error  
Offset Error  
Full-Scale Error  
±±.5  
±1  
LSB  
LSB  
mV  
mV  
% of FSR  
% of FSR  
μV/°C  
ppm  
dB  
±±.25  
+1±  
±1±  
±1  
Guaranteed monotonic by design  
All ±s loaded to DAC register  
+2  
±1  
−±.1  
All 1s loaded to DAC register  
Gain Error  
±1.5  
Zero-Scale Error Drift  
Gain Temperature Coefficient  
DC Power Supply Rejection Ratio  
DC Crosstalk (External Reference)  
±2  
±2.5  
−1±±  
1±  
Of FSR/°C  
DAC code = midscale; VDD = 3 V ± 1±%  
Due to full-scale output change;  
RL = 2 kꢀ to GND or VDD  
μV  
1±  
5
μV/mA  
μV  
Due to load current change  
Due to powering down (per channel)  
DC Crosstalk (Internal Reference)  
25  
μV  
Due to full-scale output change;  
RL = 2 kꢀ to GND or VDD  
2±  
1±  
μV/mA  
μV  
Due to load current change  
Due to powering down (per channel)  
OUTPUT CHARACTERISTICS3  
Output Voltage Range  
±
VDD  
V
Capacitive Load Stability  
2
nF  
nF  
mA  
μs  
RL = ∞  
RL = 2 kꢀ  
1±  
±.5  
3±  
4
DC Output Impedance  
Short Circuit Current  
Power-Up Time  
VDD = 3 V  
Coming out of power-down mode; VDD = 3 V  
REFERENCE INPUTS  
Reference Current  
17±  
26  
2±±  
VDD  
μA  
V
kꢀ  
VREF = VDD = 3.6 V  
Reference Input Range  
Reference Input Impedance  
REFERENCE OUTPUT  
Output Voltage  
±.75  
1.247  
1.253  
±15  
V
At ambient  
MSOP package models  
LFCSP package models  
Reference Temperature Coefficient3  
±5  
±1±  
7.5  
ppm/°C  
ppm/°C  
kꢀ  
Output Impedance  
Rev. A | Page 5 of 28  
 

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