Datasheet > AD5623RACPZ-5REEL7

AD5623RACPZ-5REEL7

更新时间： 2022-04-25 11:44:49

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
32页	967K
描述
Dual 12-/14-/16-Bit nanoDAC with 5 ppm/ C On-Chip Reference

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AD5623RACPZ-5REEL7 数据手册

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Data Sheet

AD5623R/AD5643R/AD5663R

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OUT

REFIN REFOUT

AD5623R/

AD5643R/

AD5663R

TOP VIEW

(Not to Scale)

OUT

GND

DIN

LDAC

CLR

SCLK

SYNC

NOTE:

EXPOSED PAD TIED TO GND ON

LFCSP PACKAGE.

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

V_OUT

GND

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

Ground. Reference point for all circuitry on the part.

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.

This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.

LDAC

CLR

Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are

ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V.

The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during

a write sequence, the write is aborted.

SYNC

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.

When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the

following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge,

in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.

SCLK

DIN

V_DD

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.

Data can be transferred at rates up to 50 MHz.

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge

of the serial clock input.

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with

a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

V_REFIN/V_REFOUTCommon Reference Input/Reference Output. When the internal reference is selected, this is the reference output

pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input.

Rev. F | Page 9 of 32

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