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AD5622WKSZ-1REEL7 PDF预览

AD5622WKSZ-1REEL7

更新时间: 2024-01-08 21:37:07
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器光电二极管
页数 文件大小 规格书
24页 560K
描述
2.7 V to 5.5 V, <100 uA, 8-/10-/12-Bit nanoDACs with

AD5622WKSZ-1REEL7 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:LEAD FREE, MO-203AB, SC-70, 6 PIN针数:6
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.57
Is Samacsys:N最大模拟输出电压:5.5 V
最小模拟输出电压:转换器类型:D/A CONVERTER
输入位码:BINARY输入格式:SERIAL
JESD-30 代码:R-PDSO-G6JESD-609代码:e4
长度:2 mm最大线性误差 (EL):0.1465%
湿度敏感等级:1位数:12
功能数量:1端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSSOP
封装等效代码:TSSOP6,.08封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3/5 V认证状态:Not Qualified
座面最大高度:1 mm最大稳定时间:10 µs
标称安定时间 (tstl):6 µs子类别:Other Converters
最大压摆率:0.1 mA标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:1.25 mmBase Number Matches:1

AD5622WKSZ-1REEL7 数据手册

 浏览型号AD5622WKSZ-1REEL7的Datasheet PDF文件第2页浏览型号AD5622WKSZ-1REEL7的Datasheet PDF文件第3页浏览型号AD5622WKSZ-1REEL7的Datasheet PDF文件第4页浏览型号AD5622WKSZ-1REEL7的Datasheet PDF文件第6页浏览型号AD5622WKSZ-1REEL7的Datasheet PDF文件第7页浏览型号AD5622WKSZ-1REEL7的Datasheet PDF文件第8页 
AD5602/AD5612/AD5622  
Limit at TMIN, TMAX  
Parameter  
Conditions2  
Min  
Max  
Unit  
μs  
μs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Description  
t8  
Standard mode  
Fast mode  
High speed mode  
Standard mode  
Fast mode  
High speed mode, CB = 100 pF  
High speed mode, CB = 400 pF  
Standard mode  
4
0.6  
160  
tSU;STO, setup time for a stop condition  
t9  
1000  
300  
80  
160  
300  
300  
80  
160  
1000  
300  
40  
tRDA, rise time of SDA signal  
10  
20  
t10  
t11  
t11A  
tFDA, fall time of SDA signal  
tRCL, rise time of SCL signal  
Fast mode  
High speed mode, CB = 100 pF  
High speed mode, CB = 400 pF  
Standard mode  
10  
20  
Fast mode  
High speed mode, CB = 100 pF  
High speed mode, CB = 400 pF  
Standard mode  
10  
20  
80  
1000  
tRCL1, rise time of SCL signal after a repeated start  
condition and after an acknowledge bit  
Fast mode  
300  
80  
160  
300  
300  
40  
80  
50  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
High speed mode, CB = 100 pF  
High speed mode, CB = 400 pF  
Standard mode  
10  
20  
t12  
tFCL, fall time of SCL signal  
Fast mode  
High speed mode, CB = 100 pF  
High speed mode, CB = 400 pF  
Fast mode  
10  
20  
0
4
tSP  
Pulse width of spike suppressed  
High speed mode  
0
1 See Figure 2. High speed mode timing specification applies to the AD5602-1/AD5612-1/AD5622-1 only. Standard and fast mode timing specifications apply to the  
AD5602-1/AD5612-1/AD5622-1 and AD5602-2/AD5612-2/AD5622-2.  
2 CB refers to the capacitance on the bus line.  
3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior  
of the part.  
4 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.  
TIMING DIAGRAM  
t11  
t12  
t6  
t2  
t6  
SCL  
t1  
t3  
t5  
t10  
t8  
t4  
t9  
SDA  
t7  
P
S
S
P
Figure 2. 2-Wire Serial Interface Timing Diagram  
Rev. B | Page 5 of 24  
 
 
 
 
 

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