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AD5622ACPZ-2-RL7

更新时间： 2024-02-18 14:34:29
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管转换器
页数 文件大小 规格书
24页 649K
描述
2.7 V to 5.5 V, nanoDAC&reg; with I<sup>2</sup>C Compatible Interface, Tiny SC70 Package

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AD5622ACPZ-2-RL7 技术参数

Source Url Status Check Date：2013-05-01 14:56:13.788是否无铅： 含铅
生命周期：Obsolete包装说明：HVSON,
针数：6Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.67最大模拟输出电压：5.5 V
最小模拟输出电压：转换器类型：D/A CONVERTER
输入位码：BINARY输入格式：SERIAL
JESD-30 代码：R-PDSO-N6长度：3 mm
最大线性误差 (EL)：0.1465%位数：12
功能数量：1端子数量：6
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVSON
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
座面最大高度：0.8 mm标称安定时间 (tstl)：6 µs
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子形式：NO LEAD端子节距：0.65 mm
端子位置：DUAL宽度：2 mm
Base Number Matches：1

AD5622ACPZ-2-RL7 数据手册

 浏览型号AD5622ACPZ-2-RL7的Datasheet PDF文件第4页浏览型号AD5622ACPZ-2-RL7的Datasheet PDF文件第5页浏览型号AD5622ACPZ-2-RL7的Datasheet PDF文件第6页浏览型号AD5622ACPZ-2-RL7的Datasheet PDF文件第8页浏览型号AD5622ACPZ-2-RL7的Datasheet PDF文件第9页浏览型号AD5622ACPZ-2-RL7的Datasheet PDF文件第10页 
Data Sheet  
AD5602/AD5612/AD5622  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
ADDR  
GND  
1
2
3
6
5
4
SDA  
SCL  
ADDR  
1
2
3
6
5
4
V
OUT  
AD5602/  
AD5612/  
AD5622  
AD5602/  
AD5612/  
AD5622  
SCL  
GND  
TOP VIEW  
TOP VIEW  
(Not to Scale)  
(Not to Scale)  
SDA  
V
DD  
V
V
DD  
OUT  
NOTES  
1. THE EXPOSED PAD SHOULD BE CONNECTED  
TO GROUND (GND).  
Figure 3. SC70 Pin Configuration  
Figure 4. LFCSP Pin Configuration  
Table 5. SC70 Pin Function Descriptions  
Pin No. Mnemonic Description  
Table 6. LFCSP Pin Function Descriptions  
Pin No.  
Mnemonic Description  
1
ADDR  
Three-State Address Input. Sets the two  
least significant bits (Bit A1, Bit A0) of  
the 7-bit slave address (see Table 7).  
1
ADDR  
Three-State Address Input. Sets the  
two least significant bits (Bit A1, Bit A0)  
of the 7-bit slave address (see Table 7).  
2
SCL  
Serial Clock Line. This is used in  
conjunction with the SDA line to clock  
data into or out of the 16-bit input  
register.  
2
3
GND  
VOUT  
Ground. The ground reference point for  
all circuitry on the device.  
Analog Output Voltage from the DAC.  
The output amplifier has rail-to-rail  
operation.  
3
4
SDA  
Serial Data Line. This is used in  
conjunction with the SCL line to clock  
data into or out of the 16-bit input  
register. It is a bidirectional, open-drain  
data line that should be pulled to the  
supply with an external pull-up resistor.  
Power Supply Input. These devices can be  
operated from 2.7 V to 5.5 V, and VDD  
should be decoupled to GND.  
4
5
VDD  
Power Supply Input. These devices can  
be operated from 2.7 V to 5.5 V, and VDD  
should be decoupled to GND.  
Serial Clock Line. This is used in  
conjunction with the SDA line to clock  
data into or out of the 16-bit input  
register.  
SCL  
VDD  
6
SDA  
Serial Data Line. This is used in  
5
6
GND  
VOUT  
Ground. The ground reference point for  
all circuitry on the devices.  
Analog Output Voltage from the DAC.  
The output amplifier has rail-to-rail  
operation.  
conjunction with the SCL line to clock  
data into or out of the 16-bit input  
register. It is a bidirectional, open-drain  
data line that should be pulled to the  
supply with an external pull-up resistor.  
EPAD  
Exposed Pad. The exposed pad should  
be connected to ground (GND).  
Rev. D | Page 7 of 24  
 
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