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AD5621BKS-REEL

更新时间： 2024-02-02 13:28:38
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管转换器
页数 文件大小 规格书
17页 525K
描述
IC,D/A CONVERTER,SINGLE,12-BIT,CMOS,TSSOP,6PIN

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中文翻译

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AD5621BKS-REEL 技术参数

生命周期：Obsolete包装说明：TSSOP, TSSOP6,.08
Reach Compliance Code：compliant风险等级：5.84
转换器类型：D/A CONVERTER输入位码：BINARY
JESD-30 代码：R-PDSO-G6最大线性误差 (EL)：0.02%
位数：12功能数量：1
端子数量：6最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP6,.08
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：3/5 V认证状态：Not Qualified
最大稳定时间：18 µs子类别：Other Converters
最大压摆率：0.1 mA表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUALBase Number Matches：1

AD5621BKS-REEL 数据手册

 浏览型号AD5621BKS-REEL的Datasheet PDF文件第9页浏览型号AD5621BKS-REEL的Datasheet PDF文件第10页浏览型号AD5621BKS-REEL的Datasheet PDF文件第11页浏览型号AD5621BKS-REEL的Datasheet PDF文件第13页浏览型号AD5621BKS-REEL的Datasheet PDF文件第14页浏览型号AD5621BKS-REEL的Datasheet PDF文件第15页 
AD5601/AD5611/AD5621  
Preliminary Technical Data  
GENERAL DESCRIPTION  
D/A SECTION  
SERIAL INTERFACE  
The AD5601/AD5611/AD5621 DACs are fabricated on a  
CMOS process. The architecture consists of a string DAC  
followed by an output buffer amplifier. Figure 22 shows a block  
diagram of the DAC architecture.  
The AD5601/AD5611/AD5621 have a three-wire serial  
interface (SYNC, SCLK and DIN), which is compatible with SPI,  
QSPI and MICROWIRE interface standards as well as most  
DSPs. See Figure 2 for a timing diagram of a typical write  
sequence.  
V
DD  
The write sequence begins by bringing the SYNC line low. Data  
from the DIN line is clocked into the 16-bit shift register on the  
falling edge of SCLK. The serial clock frequency can be as high  
as 30 MHz, making the AD5601/AD5611/AD5621compatible  
with high speed DSPs. On the 16th falling clock edge, the last  
data bit is clocked in and the programmed function is executed  
(i.e., a change in DAC register contents and/or a change in the  
mode of operation). At this stage, the SYNC line may be kept  
low or be brought high. In either case, it must be brought high  
for a minimum of 33 ns before the next write sequence so that a  
falling edge of SYNC can initiate the next write sequence. Since  
the SYNC buffer draws more current when VIN = 1.8 V than it  
does when VIN = 0.8 V, SYNC should be idled low between write  
sequences for even lower power operation of the part, as  
mentioned above; however, it must be brought high again just  
before the next write sequence.  
REF (+)  
RESISTOR  
NETWORK  
V
DAC REGISTER  
OUT  
REF (–ٛ)  
OUTPUT  
AMPLIFIER  
GND  
Figure 22. DAC Architecture  
Since the input coding to the DAC is straight binary, the ideal  
output voltage is given by  
where D = decimal equivalent of the binary code that is loaded  
to the DAC register.  
RESISTOR STRING  
INPUT SHIFT REGISTER  
The resistor string section is shown in Figure 21. It is simply a  
string of resistors, each of value R. The code loaded to the DAC  
register determines at which node on the string the voltage is  
tapped off to be fed into the output amplifier. The voltage is  
tapped off by closing one of the switches connecting the string  
to the amplifier. Because it is a string of resistors, it is  
guaranteed monotonic.  
The input shift register is 16 bits wide (see Figure 23). The first  
two bits are control bits that control which mode of operation  
the part is in (normal mode or any one of three power-down  
modes). There is a more complete description of the various  
modes in the Power-Down Modes section. The next sixteen bits  
are the data bits. These are transferred to the DAC register on  
the 16th falling edge of SCLK.  
OUTPUT AMPLIFIER  
The output buffer amplifier is capable of generating rail-to-rail  
voltages on its output, giving an output range of 0 V to VDD. It is  
capable of driving a load of 2 kΩ in parallel with 1000 pF to  
GND. The source and sink capabilities of the output amplifier  
can be seen in Figure 9 and Figure 10. The slew rate is 0.5 V/µs  
with a half-scale settling time of 8 µs with the output unloaded.  
DB15 (MSB)  
DBO (LSB)  
PD1  
PD0  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
DATA BITS  
NORMAL OPERATION  
1 kΩ TO GND  
0
0
1
1
0
1
0
1
100 kΩ TO GND  
THREE-STATE  
POWER-DOWN MODES  
Figure 23. Input Register Contents  
Rev. PrB | Page 12 of 17  
1...9101112131415...17

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