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AD5620CRM-3 PDF预览

AD5620CRM-3

更新时间: 2022-11-26 12:50:11
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 554K
描述
Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23

AD5620CRM-3 数据手册

 浏览型号AD5620CRM-3的Datasheet PDF文件第1页浏览型号AD5620CRM-3的Datasheet PDF文件第2页浏览型号AD5620CRM-3的Datasheet PDF文件第3页浏览型号AD5620CRM-3的Datasheet PDF文件第5页浏览型号AD5620CRM-3的Datasheet PDF文件第6页浏览型号AD5620CRM-3的Datasheet PDF文件第7页 
AD5620/AD5640/AD5660  
Parameter  
LOGIC INPUTS3  
A Grade1 B Grade1 C Grade1 Unit  
Conditions/Comments  
Input Current  
±2  
0.±  
2
±2  
0.±  
2
±2  
0.±  
2
μA max  
V max  
V min  
All digital inputs  
VDD = 5 V  
VDD = 5 V  
VINL, Input Low Voltage  
VINH, Input High Voltage  
Pin Capacitance  
POWER REQUIREMENTS  
VDD  
3
3
3
pF typ  
4.5  
5.5  
4.5  
5.5  
4.5  
5.5  
V min  
V max  
All digital inputs at 0 V or VDD  
DAC active and excluding load current  
IDD (Normal Mode)  
VDD = 4.5 V to 5.5 V  
VDD = 4.5 V to 5.5 V  
IDD (All Power-Down Modes)  
VDD = 4.5 V to 5.5 V  
VDD = 4.5 V to 5.5 V  
0.55  
1
0.55  
1
0.55  
1
mA typ  
mA max  
VIH = VDD and VIL = GND  
VIH = VDD and VIL = GND  
0.4±  
1
0.4±  
1
0.4±  
1
μA typ  
μA max  
VIH = VDD and VIL = GND  
VIH = VDD and VIL = GND  
1 Temperature range is −15°C to +105°C, typical at 25°C.  
2 Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 12± to Code 16256); AD5620 (Code 32 to Code 4064). Output  
unloaded. Linearity tested with VDD = 5.5 V. If part is operated with a VDD < 5 V, the output is clamped to VDD.  
3 Guaranteed by design and characterization; not production tested.  
Rev. A | Page 4 of 24  

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