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AD5541ABCPZ-1-RL7 PDF预览

AD5541ABCPZ-1-RL7

更新时间： 2024-02-03 14:27:41
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 输入元件光电二极管转换器
页数 文件大小 规格书
21页 1326K
描述
SERIAL INPUT LOADING, 1 us SETTLING TIME, 16-BIT DAC, PDSO8, 3 X 3 MM, ROHS COMPLIANT, MO-229WEED, LFCSP-8

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AD5541ABCPZ-1-RL7 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SON
包装说明：HVSON,针数：8
Reach Compliance Code：unknown风险等级：5.65
最大模拟输出电压：4.5 V最小模拟输出电压：
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：SERIALJESD-30 代码：S-PDSO-N8
JESD-609代码：e3长度：3 mm
最大线性误差 (EL)：0.0015%湿度敏感等级：1
位数：16功能数量：1
端子数量：8最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HVSON封装形状：SQUARE
封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：225
认证状态：COMMERCIAL座面最大高度：0.8 mm
标称安定时间 (tstl)：1 µs表面贴装：YES
温度等级：AUTOMOTIVE端子面层：MATTE TIN
端子形式：NO LEAD端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3 mmBase Number Matches：1

AD5541ABCPZ-1-RL7 数据手册

 浏览型号AD5541ABCPZ-1-RL7的Datasheet PDF文件第12页浏览型号AD5541ABCPZ-1-RL7的Datasheet PDF文件第13页浏览型号AD5541ABCPZ-1-RL7的Datasheet PDF文件第14页浏览型号AD5541ABCPZ-1-RL7的Datasheet PDF文件第16页浏览型号AD5541ABCPZ-1-RL7的Datasheet PDF文件第17页浏览型号AD5541ABCPZ-1-RL7的Datasheet PDF文件第18页 
AD5541A  
THEORY OF OPERATION  
The AD5541A is a single, 16-bit, serial input, voltage output  
DAC. It operates from a single supply ranging from 2.7 V to 5 V  
and consumes typically 125 μA with a supply of 5 V. Data is written  
to these devices in a 16-bit word format, via a 3- or 4-wire serial  
interface. To ensure a known power-up state, this part is designed  
with a power-on reset function. The output is reset to 0 V.  
SERIAL INTERFACE  
The AD5541A is controlled by a versatile 3- or 4-wire serial  
interface that operates at clock rates of up to 50 MHz and is  
compatible with LPI, QLPI, MICROWIRE, and DLP interface  
standards. The timing diagram is shown in Figure 3. The  
AD5541A has a separate serial input register from the 16-bit  
DAC register that allows preloading of a new data value into the  
serial input register without disturbing the present DAC output  
voltage.  
DIGITAL-TO-ANALOG SECTION  
The DAC architecture consists of two matched DAC sections.  
A simplified circuit diagram is shown in Figure 30. The DAC  
architecture of the AD5541A is segmented. The four MLBs of  
the 16-bit data-word are decoded to drive 15 switches, E1 to  
E15. Each switch connects one of 15 matched resistors to either  
AGND or VREF. The remaining 12 bits of the data-word drive  
the L0 to L11 switches of a 12-bit voltage mode R-2R ladder  
network.  
CL  
Input data is framed by the chip select input, . After a high-  
CL  
to-low transition on , data is shifted synchronously and  
latched into the serial input register on the rising edge of the  
serial clock, LCꢀK. After 16 data bits have been loaded into the  
CL  
serial input register, a low-to-high transition on  
contents of the shift register to the DAC register if  
ꢀDAC  
transfers the  
ꢀDAC  
is held  
is high at this point, a low-to-high transition on  
transfers the contents into the serial input register only.  
R
R
low. If  
CL  
V
OUT  
2R  
2R  
S0  
2R . . . . .  
S1 . . . . .  
2R  
2R  
E1  
2R . . . . .  
E2 . . . . .  
2R  
E15  
After a new value is fully loaded in the serial input register, it  
can be asynchronously transferred to the DAC register by  
S11  
ꢀDAC  
strobing the  
pin. Data is loaded MLB first in 16-bit  
CL  
V
REF  
words. Data can be loaded to the part only while  
is low.  
FOUR MSBs DECODED  
INTO 15 EQUAL SEGMENTS  
12-BIT R-2R LADDER  
Figure 30. DAC Architecture  
With this type of DAC configuration, the output impedance is  
independent of code, whereas the input impedance seen by the  
reference is heavily code dependent. The output voltage is  
dependent on the reference voltage, as shown in the following  
equation:  
VREF × D  
VOUT  
where:  
=
2N  
D is the decimal data-word loaded to the DAC register.  
N is the resolution of the DAC.  
For a reference of 2.5 V, the equation simplifies to the following:  
2.5 × D  
VOUT  
=
65,536  
This gives a VOUT of 1.25 V with midscale loaded and 2.5 V with  
full scale loaded to the DAC.  
The ꢀLB size is VREF/65,536.  
Rev. A | Page 14 of 20  
 
 
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