AD5539J

更新时间： 2024-01-19 01:54:07

品牌	Logo	应用领域
亚德诺 - ADI		运算放大器
页数	文件大小	规格书
16页	475K
描述
Ultrahigh Frequency Operational Amplifier

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AD5539J 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	14
Reach Compliance Code：	unknown	风险等级：	5.71
Is Samacsys：	N	商用集成电路类型：	VIDEO AMPLIFIER
JESD-30 代码：	R-GDIP-T14	JESD-609代码：	e0
长度：	19.43 mm	信道数量：	1
功能数量：	1	端子数量：	14
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	COMMERCIAL
座面最大高度：	5.08 mm	最大供电电压 (Vsup)：	10 V
最小供电电压 (Vsup)：	4.5 V	表面贴装：	NO
温度等级：	MILITARY	端子面层：	TIN LEAD
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

AD5539J 数据手册

AD5539

frequency. Both of these circuit techniques add a large amount

of leading phase shift at the crossover frequency, greatly aiding

stability.

T he lag network (R_LAG, C_LAG) increases the feedback attenua-

tion, i.e., the amplifier operates at a higher noise gain, above

some frequency, typically one-tenth of the crossover frequency.

As an example, to achieve a noise gain of 5 at frequencies above

44 MHz, for the circuit of Figure 15, would require a network

of:

R_LAG

(3)

4R1 / R2 – 1

(

)

and . . .

C_LAG

2 π R_LAG44 × 10⁶

(4)

(

)

Figure 18. Response of the (Figure 17) Inverter Circuit

without a Lag Com pensation Network

It is worth noting that an R_LAGresistor may be used alone, to in-

crease the noise gain above 5 at all frequencies. However, this

approach has the disadvantage of also increasing the dc offset

and low frequency noise errors by an amount equal to the in-

crease in gain, in this case, by a factor of 5.

A lag network (Figure 15) can be added to improve the response

of this circuit even further as shown in Figures 19 and 20. In al-

most all cases, it is imperative to make capacitor C_LEADadjust-

able; in some cases, C_LAGmust also be variable. Otherwise,

component and circuit capacitance variations will dominate cir-

cuit performance.

SO ME P RACTICAL CIRCUITS

T he preceding general principles may now be applied to some

actual circuits.

A Gener al P ur pose Inver ter Cir cuit

Figure 17 is a general purpose inverter circuit operating at a

gain of –2.

For this circuit, the total capacitance at the inverting input is ap-

proximately 3 pF; therefore, C_LEADfrom Equations 1 and 2

needs to be approximately 1.5 pF. As shown in Figure 17, a

small trimmer is used to optimize the frequency response of this

circuit. Without a lag compensation network, the noise gain of

the circuit is 3.0 and, as shown in Figure 18, the output ampli-

tude remains within ±0.5 dB to 170 MHz and the –3 dB band-

width is 200 MHz.

Figure 19. Response of the (Figure 17) Inverter Circuit

with an R_LAGCom pensation Network Em ployed

Figure 17. A General Purpose Inverter Circuit

Figure 20. Response of the (Figure 17) Inverter Circuit

with an R_LAGand a C_LAGCom pensation Network

Em ployed

–8–

REV. B

1...5 6 789 10 11...16

中文翻译

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与AD5539J相关器件

型号	品牌	描述	获取价格	数据表
AD5539JCHIPS	ADI	AD5539JCHIPS	获取价格
AD5539JN	ADI	Ultrahigh Frequency Operational Amplifier	获取价格
AD5539JQ	ADI	Ultrahigh Frequency Operational Amplifier	获取价格
AD5539S	ADI	Ultrahigh Frequency Operational Amplifier	获取价格
AD5539SCHIPS	ADI	AD5539SCHIPS	获取价格
AD5539SQ	ADI	Ultrahigh Frequency Operational Amplifier	获取价格

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