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AD5539J PDF预览

AD5539J

更新时间: 2024-01-23 07:49:21
品牌 Logo 应用领域
亚德诺 - ADI 运算放大器
页数 文件大小 规格书
16页 475K
描述
Ultrahigh Frequency Operational Amplifier

AD5539J 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:14
Reach Compliance Code:unknown风险等级:5.71
Is Samacsys:N商用集成电路类型:VIDEO AMPLIFIER
JESD-30 代码:R-GDIP-T14JESD-609代码:e0
长度:19.43 mm信道数量:1
功能数量:1端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:COMMERCIAL
座面最大高度:5.08 mm最大供电电压 (Vsup):10 V
最小供电电压 (Vsup):4.5 V表面贴装:NO
温度等级:MILITARY端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

AD5539J 数据手册

 浏览型号AD5539J的Datasheet PDF文件第9页浏览型号AD5539J的Datasheet PDF文件第10页浏览型号AD5539J的Datasheet PDF文件第11页浏览型号AD5539J的Datasheet PDF文件第13页浏览型号AD5539J的Datasheet PDF文件第14页浏览型号AD5539J的Datasheet PDF文件第15页 
AD5539  
Figure 38. Differential Phase vs. Ram p Am plitude  
Figure 35. Differential Gain and Phase Measurem ent  
Circuit  
MEASURING AD 5539 SETTLING TIME  
Measuring the very rapid settling times associated with AD5539  
can be a real problem for the designer; proper component layout  
must be used and appropriate test equipment selected. In addi-  
tion, both cable dispersion (a function of cable losses) and the  
quality of termination (SWR) directly affect the measurement.  
T he circuit of Figure 39 was used to make a “brute force”  
AD5539 settling time measurement. T he fixture containing the  
circuit was connected directly—using a male BNC connector  
(but no cable)—onto the front of a 50 input oscilloscope  
preamp. A digital mainframe was then used to capture, average,  
and expand the error signal. Most of the small-scale waveform  
aberrations shown on the figure were caused by the oscilloscope  
itself, especially the glitch at 15 ns. T he pulse source used for  
this measurement was an EH-SPG2000 pulse generator set for a  
1 ns rise-time; it was coupled directly to the circuit using 18" of  
microwave 50 hard line.  
Figure 36. Differential Gain and Phase Test Setup  
Figure 37. Differential Gain vs. Ram p Am plitude  
Figure 39. AD5539 Settling Tim e Test Circuit  
–12–  
REV. B  

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