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AD5535

更新时间： 2024-01-06 17:00:11
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
16页 395K
描述
32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V

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AD5535 技术参数

Source Url Status Check Date：2013-05-01 14:56:13.209是否无铅： 含铅
是否Rohs认证： 符合生命周期：Contact Manufacturer
包装说明：LBGA, BGA124,14X14,40针数：124
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.3
最大模拟输出电压：224 V最小模拟输出电压：1 V
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：SERIALJESD-30 代码：S-PBGA-B124
JESD-609代码：e1长度：15 mm
湿度敏感等级：3位数：14
功能数量：1端子数量：124
最高工作温度：85 °C最低工作温度：-10 °C
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA124,14X14,40封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE峰值回流温度（摄氏度）：260
座面最大高度：1.7 mm标称安定时间 (tstl)：60 µs
最大压摆率：20 mA标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：15 mmBase Number Matches：1

AD5535 数据手册

 浏览型号AD5535的Datasheet PDF文件第9页浏览型号AD5535的Datasheet PDF文件第10页浏览型号AD5535的Datasheet PDF文件第11页浏览型号AD5535的Datasheet PDF文件第13页浏览型号AD5535的Datasheet PDF文件第14页浏览型号AD5535的Datasheet PDF文件第15页 
AD5535  
Preliminary Technical Data  
AD5535 to PIC16C6X/7X  
ADSP-2101/  
ADSP-2103*  
AD5535*  
The PIC16C6x/7x synchronous serial port (SSP) is configured  
as an SPI master with the clock polarity bit = 0. This is done by  
writing to the synchronous serial port control register  
SCLK  
SCLK  
D
DT  
IN  
TFS  
SYNC  
(SSPCON). See the PIC16/17 Microcontroller User Manual. In  
*ADDITIONAL PINS OMITTED FOR CLARITY  
SYNC  
this example, I/O port RA1 is being used to pulse  
and  
enable the serial port of the AD5535. This microcontroller  
transfers only eight bits of data during each serial transfer  
operation; therefore, three consecutive write operations are  
necessary to transmit 19 bits of data. Data is transmitted MSB  
first. It is important to left-justify the data in the SPDR register  
so that the first 19 bits transmitted contain valid data. RA1 must  
be pulled low to start a transfer. It is taken high and pulled low  
again before any further write cycles can take place. Figure 13  
shows the connection diagram.  
Figure 11. AD5535 to ADSP-2101/ADSP-2103 Interface  
AD5535 to MC68HC11  
The serial peripheral interface (SPI) on the MC68HC11 is  
configured for master mode (MSTR = 1), clock polarity bit  
(CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is  
configured by writing to the SPI control register (SPCR)—see  
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK  
of the AD5535 and the MOSI output drives the serial data line  
SYNC  
(DIN) of the AD5535. The  
line (PC7). When data is being transmitted to the AD5535, the  
SYNC  
signal is derived from a port  
PIC16C6x/7x*  
AD5535*  
SCLK  
SCK/RC3  
line is taken low (PC7).  
D
SDI/RC4  
RA1  
IN  
SYNC  
Data appearing on the MOSI output is valid on the falling edge  
of SCK. The 68HC11 transfers only eight bits of data during  
each serial transfer operation; therefore, three consecutive write  
operations are necessary to transmit 19 bits of data. Data is  
transmitted MSB first. It is important to left-justify the data in  
the SPDR register so that the first 19 bits transmitted contain  
valid data. PC7 must be pulled low to start a transfer. It is taken  
high and pulled low again before any further write cycles can  
take place. See Figure 12.  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 13. AD5535 to PIC16C6x/7x Interface  
AD5535 to 8051  
The AD5535 requires a clock synchronized to the serial data.  
The 8051 serial interface must, therefore, be operated in  
Mode 0. In this mode, serial data exits the 8051 through RxD,  
SYNC  
and a shift clock is output on TxD. The  
signal is derived  
from a port line (P1.1). Figure 14 shows how the 8051 is  
connected to the AD5535. Because the AD5535 shifts data out  
on the rising edge of the shift clock and latches data in on the  
falling edge, the shift clock must be inverted. Note also that the  
AD5535 requires its data with the MSB first. Because the 8051  
outputs the LSB first, the transmit routine must take this into  
account.  
MC68HC11*  
AD5535*  
SCLK  
SCK  
D
MOSI  
PC7  
IN  
SYNC  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 12. AD5535 to MC68HC11 Interface  
8051*  
AD5535*  
SCLK  
TxD  
RxD  
P1.1  
D
IN  
SYNC  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 14. AD5535 to 8051 Interface  
Rev. PrE | Page 12 of 16  
 
 
 
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