AD5532B
PIN FUNCTION DESCRIPTIONS
Mnemonic
Description
AGND (1–2)
AVCC (1–2)
Analog GND Pins
Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
VDD Supply Pins. Voltage range from 8 V to 16.5 V.
VSS Supply Pins. Voltage range from –4.75 V to –16.5 V.
Digital GND Pins
V
V
DD (1–4)
SS (1–4)
DGND
DVCC
DAC_GND (1–2)
REF_IN
Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.
Reference GND Supply for all the DACs
Reference Voltage for Channels 0–31
REF_OUT
Reference Output Voltage
V
OUT (0–31)
Analog Output Voltages from the 32 Channels
VIN
Analog Input Voltage. Connect this to AGND if operating in DAC mode only.
Parallel Interface. 5-address pins for 32 channels. A4 = MSB of channel address. A0 = LSB.
Parallel Interface. Control input that allows all 32 channels to acquire VIN simultaneously.
A4–A11, A02
CAL1
CS/SYNC
This pin is both the active low chip select pin for the parallel interface and the frame synchronization pin for
the serial interface.
Parallel Interface. Write pin. Active low. This is used in conjunction with the CS pin to address the device
WR1
using the parallel interface.
OFFSET_SEL1
SCLK2
Parallel Interface. Offset select pin. Active high. This is used to select the offset channel.
Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in ISHA mode).
Data Input for Serial Interface. Data must be valid on the falling edge of SCLK.
2
DIN
DOUT
Output from the DAC Registers for Readback. Data is clocked out on the rising edge of SCLK and is valid
on the falling edge of SCLK.
SER/PAR1
OFFS_IN
This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low,
the parallel interface will be used. If it is tied high, the serial interface will be used.
Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to
this pin if the user wants to drive this pin with the offset channel.
OFFS_OUT
Offset Output. This is the acquired/programmed offset voltage that can be tied to OFFS_IN to offset the span.
BUSY
This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns
high when the acquisition operation is complete.
If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the
gain/offset stage is switched directly to VIN. The addressed channel begins to acquire VIN on the rising edge
of TRACK. See TRACK Input section for further information. This input can also be used as a means of
resetting the complete device to its power-on-reset conditions. This is achieved by applying a low going
pulse of between 90 ns and 200 ns to this pin. See section on RESET Function for further details.
TRACK/RESET2
NOTES
1Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.
2Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
OUTPUT
VOLTAGE
V
OUT
GAIN ERROR +
OFFSET ERROR
FULL-SCALE
ERROR RANGE
IDEAL
TRANSFER
FUNCTION
IDEAL TRANSFER
ACTUAL
TRANSFER
FUNCTION
FUNCTION
DAC CODE
OFFSET
ERROR
OFFSET
RANGE
0V
70mV
2.96 3V
V
IN
0
16k
LOWER
DEAD BAND
UPPER
DEAD BAND
Figure 6. DAC Transfer Function (OFFS_IN = 0)
Figure 7. ISHA Transfer Function
–8–
REV. A
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