Datasheet > AD5533B

AD5533B

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	354K
描述
32-Channel Precision Infinite Sample-and-Hold

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AD5533B 数据手册

AD5533B

TIMING CHARACTERISTICS

PARALLEL INTERFACE

Limit at T_MIN, T_MAX

Parameter^{1, 2}

(B Version)

Unit

Conditions/Comments

t₁

t₂

t₃

t₄

t₅

t₆

ns min

CS to WR Setup Time

CS to WR Hold Time

CS Pulsewidth Low

WR Pulsewidth Low

A4–A0, CAL, OFFS_SEL to WR Setup Time

A4–A0, CAL, OFFS_SEL to WR Hold Time

NOTES

¹See Parallel Interface Timing Diagram.

²Guaranteed by design and characterization, not production tested.

Speciﬁcations subject to change without notice.

SERIAL INTERFACE

Limit at T_MIN, T_MAX

Parameter^{1, 2}

(B Version)

Unit

Conditions/Comments

f_CLKIN

t₁

t₂

t₃

t₄

t₅

t₆

t₇₃

t₈₃

t₉

MHz max

ns min

ns max

ns min

SCLK Frequency

SCLK High Pulsewidth

SCLK Low Pulsewidth

SYNC Falling Edge to SCLK Falling Edge Setup Time

SYNC Low Time

D_INSetup Time

D_INHold Time

SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback

SCLK Rising Edge to D_OUTValid

SCLK Falling Edge to D_OUTHigh Impedance

10th SCLK Falling Edge to SYNC Falling Edge for Readback

SCLK Falling Edge to SYNC Falling Edge Setup Time for

Readback

400

t₁₀

t₁₁

NOTES

¹See Serial Interface Timing Diagrams.

²Guaranteed by design and characterization, not production tested.

³These numbers are measured with the load circuit of Figure 2.

⁴SYNC should be taken low while SCLK is low for readback.

Speciﬁcations subject to change without notice.

PARALLEL INTERFACE TIMING DIAGRAM

200␮A

OUTPUT

1.6V

50pF

200␮A

A4–A0, CAL,

OFFS SEL

Figure 1. Parallel Write (ISHA Mode Only)

Figure 2. Load Circuit for D_OUTTiming Speciﬁcations

–4–

REV. A

1 2 345 6 7...16

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