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AD5453YUJZ-REEL7 PDF预览

AD5453YUJZ-REEL7

更新时间: 2024-01-01 22:47:26
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器光电二极管
页数 文件大小 规格书
28页 725K
描述
8-/10-/12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface

AD5453YUJZ-REEL7 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:VSSOP, TSSOP8,.1针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.54
Is Samacsys:N转换器类型:D/A CONVERTER
输入位码:BINARY输入格式:SERIAL
JESD-30 代码:R-PDSO-G8JESD-609代码:e4
长度:2.9 mm最大线性误差 (EL):0.0122%
湿度敏感等级:1位数:14
功能数量:1端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSSOP
封装等效代码:TSSOP8,.1封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3/5 V认证状态:Not Qualified
座面最大高度:1 mm最大稳定时间:0.11 µs
标称安定时间 (tstl):0.18 µs子类别:Other Converters
最大压摆率:0.01 mA标称供电电压:3.6 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:1.6 mmBase Number Matches:1

AD5453YUJZ-REEL7 数据手册

 浏览型号AD5453YUJZ-REEL7的Datasheet PDF文件第4页浏览型号AD5453YUJZ-REEL7的Datasheet PDF文件第5页浏览型号AD5453YUJZ-REEL7的Datasheet PDF文件第6页浏览型号AD5453YUJZ-REEL7的Datasheet PDF文件第8页浏览型号AD5453YUJZ-REEL7的Datasheet PDF文件第9页浏览型号AD5453YUJZ-REEL7的Datasheet PDF文件第10页 
Data Sheet  
AD5450/AD5451/AD5452/AD5453  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
I
1
1
2
3
4
8
7
6
5
R
FB  
R
1
2
3
4
8
7
6
5
I
1
OUT  
FB  
OUT  
AD5450/  
AD5451/  
AD5452/  
AD5453  
AD5453  
V
GND  
REF  
GND  
V
V
REF  
DD  
TOP VIEW  
(Not to Scale)  
V
SCLK  
SDIN  
DD  
SCLK  
SDIN  
SYNC  
SYNC  
Figure 3. 8-Lead TSOT Pin Configuration  
NOTES  
1. THE EXPOSED PAD MUST BE  
CONNECTED TO GROUND.  
I
1
1
2
3
4
8
7
6
5
R
FB  
OUT  
GND  
V
V
REF  
DD  
AD5452/  
AD5453  
Figure 5. 8-Lead LFCSP Pin Configuration  
SCLK  
SDIN  
SYNC  
Figure 4. 8-Lead MSOP Pin Configuration  
Table 4. Pin Function Descriptions  
Pin No1  
TSOT MSOP LFCSP Mnemonic Description  
1
8
8
RFB  
DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external  
amplifier output.  
2
3
4
7
6
5
7
6
5
VREF  
VDD  
SYNC  
DAC Reference Voltage Input.  
Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V.  
Active Low Control Input. This is the frame synchronization signal for the input data. Data is  
loaded to the shift register upon the active edge of the following clocks.  
5
6
4
3
4
3
SDIN  
SCLK  
GND  
Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial  
clock input. By default, in power-up mode data is clocked into the shift register upon the falling  
edge of SCLK. The control bits allow the user to change the active edge to a rising edge.  
Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge  
of the serial clock input. Alternatively, by means of the serial control bits, the device can be  
configured such that data is clocked into the shift register upon the rising edge of SCLK.  
7
2
2
Ground Pin.  
8
1
1
IOUT  
1
DAC Current Output.  
N/A  
N/A  
EPAD  
EPAD  
Exposed pad must be connected to ground.  
1 N/A = not applicable.  
Rev. G | Page 7 of 28  
 

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