PRELIMINARY TECHNICAL DATA
AD5424/AD5433/AD5445
T E R M I N O L O G Y
In t er m od u la t ion D ist or t ion
Rela tive Accu r a cy
T he DAC is driven by two combinded sine waves
references of frequencies fa and fb. Distortion products are
produced at sum and difference frequencies of mfa±nfb
where m, n = 0, 1, 2, 3... Intermodulation terms are those
for which m or n is not equal to zero. T he second order
terms include (fa +fb) and (fa - fb) and the third order
terms are (2fa + fb), (2fa -fb), (f+2fa + 2fb) and (fa -
2fb). IMD is defined as
Relative accuracy or endpoint nonlinearity is a measure of
the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is
measured after adjusting for zero and full scale and is
normally expressed in LSBs or as a percentage of full scale
reading.
D iffer en t ia l Non lin ea r it y
Differential nonlinearity is the difference between the
measured change and the ideal 1 LSB change between any
two adjacent codes. A specified differential nonlinearity of
±1 LSB max over the operating temperature range ensures
monotonicity.
IMD = 20log (rms sum of the sum and diff distortion products)
rms amplitude of the fundamental
C om p lia n ce Volta ge Ra n ge
T he maximum range of (output) terminal voltage for
which the device will provide the specified characteristics.
G a in E r r or
Gain error or full-scale error is a measure of the output
error between an ideal DAC and the actual device output.
For these DACs, ideal maximum output is VREF – 1 LSB.
Gain error of the DACs is adjustable to zero with external
resistance.
G E NE R AL D E S C R IP T IO N
D AC Section
T he AD5424, AD5433 and AD5445 are 8, 10 and 12 bit
current output DACs consisting of a standard inverting R-
2R ladder configuration. A simplified diagram for the 8-
Bit AD5424 is shown in Figure 3. T he feedback resistor
RFB has a value of R. T he value of R is typically 10kΩ
(minimum 8kΩ and maximum 12kΩ). If IOUT 1 and IOUT 2
are kept at the same potential, a constant current flows in
each ladder leg, regardless of digital input code.
T herefore, the input resistance presented at VREF is always
constant.
O u tp u t Lea ka ge C u r r en t
Output leakage current is current which flows in the DAC
ladder switches when these are turned off. For the IOUT 1
terminal, it can be measured by loading all 0s to the DAC
and measuring the IOUT 1 current. Minimum current will
flow in the IOUT 2 line when the DAC is loaded with all 1s
O u t p u t C a p a cit a n ce
Capacitance from IOUT 1 or IOUT 2 to AGND.
O u tp u t C u r r en t Settlin g T im e
T his is the amount of time it takes for the output to settle
to a specified level for a full scale input change. For these
devices, it is specifed with a 100 Ω resistor to ground.
R
R
R
V
REF
2R
S1
2R
S2
2R
S3
2R
S8
2R
D igital to Analog Glitch lm pulse
R
R
A
FB
T he amount of charge injected from the digital inputs to
the analog output when the inputs change state. T his is
normally specified as the area of the glitch in either
pA-secs or nV-secs depending upon whether the glitch is
measured as a current or voltage signal.
I
OUT1
I
OUT 2
DAC DATA LATCHES
AND DRIVERS
Figure 3. Sim plified Ladder
D igit a l F eed t h r ou gh
Access is provided to the VREF, RFB, IOUT 1 and IOUT 2
terminals of the DAC, making the device extremely
versatile and allowing it to be configured in several
different operating modes, for example, to provide a
unipolar output, bipolar output or in single supply modes
of operation. in unipolar mode or four quadrant
multiplication in bipolar mode.
When the device is not selected, high frequency logic
activity on the device digital inputs is capacitivelly coupled
through the device to show up as noise on the IOUT pins
and subsequently into the following circuitry. T his noise is
digital feedthrough.
M u ltip lyin g F eed th r ou gh E r r or
T his is the error due to capacitive feedthrough from the
DAC reference input to the DAC IOUT 1 terminal, when all
o0s are loaded to the DAC.
Un ipolar M ode
Using a single op amp, these devices can easily be
configured to provide 2 quadrant multiplying operation or
a unipolar output voltage swing as shown in Figure 4.
H a r m on ic D ist or t ion
T he DAC is driven by an ac reference. T he ratio of the
rms sum of the harmonics of the DAC output to the
fundamental value is the T HD. Usually only the lower
order harmonices are included, such as second to fifth.
When an output amplifier is connected in unipolar mode,
the output voltage is given by:
VOUT = -D/2^n x VREF
2
2
2
2
T HD = 20log
√
(V2 + V3 + V4 + V5
)
Where D is the fractional representation of the digital
word loaded to the DAC and n is the resolution of the
D AC .
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