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AD5381BSTZ-3 PDF预览

AD5381BSTZ-3

更新时间： 2024-01-08 09:29:04
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
41页 845K
描述
40-Channel 3 V/5 V Single-Supply 12-Bit Voltage-Output DAC

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中文翻译

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AD5381BSTZ-3 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LFQFP, QFP100,.63SQ,20针数：100
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.35
最大模拟输出电压：3.6 V最小模拟输出电压：
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：PARALLEL, WORDJESD-30 代码：S-PQFP-G100
JESD-609代码：e3长度：14 mm
最大线性误差 (EL)：0.0244%湿度敏感等级：3
位数：12功能数量：1
端子数量：100最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP100,.63SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3/3.3,3/5 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大稳定时间：8 µs标称安定时间 (tstl)：6 µs
子类别：Other Converters标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：14 mmBase Number Matches：1

AD5381BSTZ-3 数据手册

 浏览型号AD5381BSTZ-3的Datasheet PDF文件第32页浏览型号AD5381BSTZ-3的Datasheet PDF文件第33页浏览型号AD5381BSTZ-3的Datasheet PDF文件第34页浏览型号AD5381BSTZ-3的Datasheet PDF文件第36页浏览型号AD5381BSTZ-3的Datasheet PDF文件第37页浏览型号AD5381BSTZ-3的Datasheet PDF文件第38页 
AD5381  
Data Sheet  
APPLICATIONS INFORMATION  
Alternatively, a load switch such as the ADP196 can be used to  
delay the first power supply until the second power supply turns  
on. Figure 41 shows a typical configuration using the ADP196.  
In this case, the AVDD is applied first. This voltage does not  
appear at the AVDD pin of the AD5381 until the DVDD is  
applied and brings the EN pin high. The result is that the AVDD  
and DVDD are both applied to the AD5381 at the same time.  
POWER SUPPLY DECOUPLING  
In any circuit where accuracy is important, careful considera-  
tion of the power supply and ground return layout helps to  
ensure the rated performance. The printed circuit board on  
which the AD5381 is mounted should be designed so that the  
analog and digital sections are separated and confined to  
certain areas of the board. If the AD5381 is in a system where  
multiple devices require an AGND-to-DGND connection, the  
connection should be made at one point only, a star ground  
point established as close to the device as possible.  
Table 18. Power Supply Sequencing  
First  
Power  
Supply  
Second  
Power  
Supply  
Recommended Operation  
See Figure 39  
See Figure 40  
For supplies with multiple pins (AVDD, DVDD), these pins  
should be tied together. The AD5381 should have ample supply  
bypassing of 10 µF in parallel with 0.1 µF on each supply,  
located as close to the package as possible and ideally right  
up against the device. The 10 µF capacitors are the tantalum  
bead type. The 0.1 µF capacitor should have low effective series  
resistance (ESR) and effective series inductance (ESI), like the  
common ceramic types that provide a low impedance path to  
ground at high frequencies, to handle transient currents due to  
internal logic switching.  
AVDD = 3 V DVDD ≥ 3 V  
DVDD = 3 V AVDD ≥ 3 V  
AVDD =  
DVDD  
DVDD =  
AVDD  
See Figure 39; this operation  
assumes separate analog and  
digital supplies.  
DVDD =  
AVDD  
AVDD =  
DVDD  
See Figure 40; this operation  
assumes separate analog and  
digital supplies.  
AVDD = 5 V DVDD = 3 V  
DVDD = 5 V AVDD = 3 V  
See Figure 4±  
Hardware reset or see Figure 42  
AVDD = 3V  
DVDD ≥ 3V  
The power supply lines of the AD5381 should use as large a  
trace as possible to provide low impedance paths and reduce  
the effects of glitches on the power supply line. Fast switching  
signals such as clocks should be shielded with digital ground  
to avoid radiating noise to other parts of the board, and should  
never be run near the reference inputs. A ground line routed  
between the DIN and SCLK lines will help reduce crosstalk  
between them (this is not required on a multilayer board  
because there will be a separate ground plane, but separat-  
ing the lines will help). It is essential to minimize noise on  
the REFOUT/REFIN line.  
SD103C OR  
EQUIVALENT  
AVDD  
DVDD  
DGND  
AD5381  
DAC  
GND  
SIGNAL  
GND  
AGND  
Avoid crossover of digital and analog signals. Traces on  
opposite sides of the board should run at right angles to  
each other. This reduces the effects of feedthrough through  
the board. A micro-strip technique is by far the best, but is  
not always possible with a double-sided board. In this tech-  
nique, the component side of the board is dedicated to the  
ground plane while signal traces are placed on the solder side.  
Figure 39. AVDD First Followed by DVDD  
AVDD ≥ 3V  
DVDD = 3V  
SD103C OR  
EQUIVALENT  
POWER SUPPLY SEQUENCING  
AVDD  
DVDD  
DGND  
For proper operation of the AD5381, apply DVDD first and  
then AVDD either simultaneously or within 10 ms of DVDD.  
This sequence ensures that the power-on reset circuitry sets the  
registers to their default values and keeps the analog outputs at  
0 V until a valid write operation takes place. When AVDD  
cannot be applied within 10 ms of DVDD, issue a hardware  
reset. This triggers the power-on reset circuitry and loads the  
default register values. In cases where the initial power supply  
has the same or a lower voltage than the second power supply, a  
Schottky diode can be used to temporarily supply power until  
the second power supply turns on. Table 18 lists the power  
supply sequences and the recommended diode connection.  
AD5381  
DAC  
GND  
SIGNAL  
AGND  
GND  
Figure 40. DVDD First Followed by AVDD  
Rev. E | Page 34 of 40  
 
 
 
 
 
 
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中文翻译

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AD5381BSTZ-3 替代型号

型号 品牌 替代类型 描述 数据表
AD5381BST-3-REEL ADI

类似代替

 		40-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC
AD5381BST-3 ADI

完全替代

 		40-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC

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AD5381BSTZ-5-REEL ADI 40-Channel 3 V/5 V Single-Supply 12-Bit Voltage-Output DAC

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AD5382 ADI 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC

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AD5382BST-3 ADI 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC

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AD5382BST-3-REEL ADI 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC

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