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AD5372_15 PDF预览

AD5372_15

更新时间: 2022-02-26 12:58:04
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
29页 722K
描述
32-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC

AD5372_15 数据手册

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AD5372/AD5373  
AD53721  
B Version  
AD53731  
B Version  
Parameter  
Unit  
Test Conditions/Comments2  
POWER REQUIREMENTS  
DVCC  
VDD  
VSS  
2.5/5.5  
9/16.5  
−16.5/−4.5  
2.5/5.5  
9/16.5  
−16.5/−4.5  
V min/V max  
V min/V max  
V min/V max  
Power Supply Sensitivity2  
∆Full Scale/∆VDD  
∆Full Scale/∆VSS  
∆Full Scale/∆DVCC  
DICC  
−75  
−75  
−90  
2
16  
18  
−75  
−75  
−90  
2
16  
18  
dB typ  
dB typ  
dB typ  
mA max  
mA max  
mA max  
mA max  
mA max  
DVCC = 5.5 V, VIH = DVCC, VIL = GND  
IDD  
Outputs unloaded, DAC outputs = 0 V  
Outputs unloaded, DAC outputs = full scale  
Outputs unloaded, DAC outputs = 0 V  
Outputs unloaded, DAC outputs = full scale  
Bit 0 in the control register is 1  
ISS  
−16  
−18  
−16  
−18  
Power-Down Mode  
DICC  
IDD  
ISS  
5
35  
−35  
250  
130  
5
35  
−35  
250  
130  
μA typ  
μA typ  
μA typ  
mW typ  
°C max  
Power Dissipation (Unloaded)  
Junction Temperature3  
VSS = −8 V, VDD = 9.5 V, DVCC = 2.5 V  
TJ = TA + PTOTAL × θJA  
1 Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.  
2 Guaranteed by design and characterization; not production tested.  
3 θJA represents the package thermal impedance.  
AC CHARACTERISTICS  
DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M),  
offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.  
Table 3.  
Parameter  
DYNAMIC PERFORMANCE1  
B Version  
Unit  
Test Conditions/Comments  
Output Voltage Settling Time  
20  
30  
1
μs typ  
μs max  
Full-scale change  
DAC latch contents alternately loaded with all 0s and all 1s  
Slew Rate  
V/μs typ  
nV-s typ  
mV max  
dB typ  
nV-s typ  
nV-s typ  
nV-s typ  
nV/√Hz typ  
Digital-to-Analog Glitch Energy  
Glitch Impulse Peak Amplitude  
Channel-to-Channel Isolation  
DAC-to-DAC Crosstalk  
Digital Crosstalk  
Digital Feedthrough  
5
10  
100  
10  
0.2  
0.02  
250  
VREF0, VREF1 = 2 V p-p, 1 kHz  
Effect of input bus activity on DAC output under test  
VREF0 = VREF1 = 0 V  
Output Noise Spectral Density @ 10 kHz  
1 Guaranteed by design and characterization; not production tested.  
Rev. C | Page 5 of 28  
 

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