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AD5347BRU-REEL

更新时间： 2024-01-01 20:35:37
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 1184K
描述
2.5 V to 5.5 V, Parallel Interface 2.5 V to 5.5 V, Parallel Interface

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AD5347BRU-REEL 数据手册

 浏览型号AD5347BRU-REEL的Datasheet PDF文件第6页浏览型号AD5347BRU-REEL的Datasheet PDF文件第7页浏览型号AD5347BRU-REEL的Datasheet PDF文件第8页浏览型号AD5347BRU-REEL的Datasheet PDF文件第10页浏览型号AD5347BRU-REEL的Datasheet PDF文件第11页浏览型号AD5347BRU-REEL的Datasheet PDF文件第12页 
AD5346/AD5347/AD5348  
AD5348 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
V
GH  
EF  
1
38  
37  
36  
35  
34  
33  
32  
31  
30  
PD  
REF  
V
2
CLR  
REF  
V
V
CD  
3
REF  
40 39 38 37 36 35 34 33 32 31  
GAIN  
WR  
4
V
V
V
V
V
A
B
C
D
1
2
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
DD  
AB  
A
OUT  
OUT  
OUT  
OUT  
RD  
CS  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
5
REF  
RD  
CS  
V
6
OUT  
12-BIT  
3
11  
10  
9
AD5348  
TOP VIEW  
(Not to Scale)  
V
V
V
B
C
D
7
DB  
11  
OUT  
OUT  
OUT  
4
12-BIT  
8
DB  
DB  
10  
9
5
AGND  
AGND  
AD5348  
TOP VIEW  
(Not to Scale)  
9
6
8
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
29 DB  
AGND  
8
V
E
F
7
OUT  
7
28  
DB  
V
E
7
OUT  
V
8
OUT  
6
27 DB  
V
F
6
OUT  
V
G
9
OUT  
5
DB  
26  
25  
5
V
G
OUT  
V
H
10  
OUT  
4
DB  
V
H
4
3
OUT  
11 12 13 14 15 16 17 18 19 20  
DGND  
BUF  
24 DB  
23 DB  
2
1
DB  
DB  
22  
21  
LDAC  
A0  
0
Figure 10. AD5348 Pin Configuration—LFCSP  
20 A2  
A1  
Figure 9. AD5348 Pin Configuration—TSSOP  
Table 7. AD5348 Pin Function Descriptions  
Pin Number  
TSSOP LFCSP Mnemonic Function  
1
2
3
4
35  
36  
37  
VREFGH  
VREFEF  
VREFCD  
Reference Input for DACs G and H.  
Reference Input for DACs E and F.  
Reference Input for DACs C and D.  
Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a  
10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP package must be at  
the same potential.  
38, 39 VDD  
5
6–9,  
40  
1–4,  
VREFAB  
VOUT  
Reference Input for DACs A and B.  
Output of DAC X. Buffered output with rail-to-rail operation.  
X
11–14  
7–10  
10  
15  
16  
17  
5, 6  
11  
12  
AGND  
DGND  
BUF  
Analog Ground. Ground reference for analog circuitry.  
Digital Ground. Ground reference for digital circuitry.  
Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.  
Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows  
all DAC outputs to be simultaneously updated.  
13  
LDAC  
18  
19  
20  
21–32  
33  
14  
15  
16  
A0  
A1  
A2  
LSB Address Pin. Selects which DAC is to be written to.  
Address Pin. Selects which DAC is to be written to.  
MSB Address Pin. Selects which DAC is to be written to.  
Twelve Parallel Data Inputs. DB11 is the MSB of these 12 bits.  
Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with  
RD to read back data from a DAC.  
17–28 DB0–DB11  
29  
CS  
34  
35  
36  
37  
38  
30  
31  
32  
33  
34  
RD  
Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.  
Active Low Write Input. Used in conjunction with CS to write data to the parallel interface.  
WR  
GAIN  
CLR  
PD  
Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF  
Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.  
Power-Down Pin. This active low control pin puts all DACs into power-down mode.  
.
Rev. 0 | Page 9 of 24  
 
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