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AD5347BRU-REEL

更新时间： 2024-02-14 07:28:18
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 1184K
描述
2.5 V to 5.5 V, Parallel Interface 2.5 V to 5.5 V, Parallel Interface

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AD5347BRU-REEL 数据手册

 浏览型号AD5347BRU-REEL的Datasheet PDF文件第4页浏览型号AD5347BRU-REEL的Datasheet PDF文件第5页浏览型号AD5347BRU-REEL的Datasheet PDF文件第6页浏览型号AD5347BRU-REEL的Datasheet PDF文件第8页浏览型号AD5347BRU-REEL的Datasheet PDF文件第9页浏览型号AD5347BRU-REEL的Datasheet PDF文件第10页 
AD5346/AD5347/AD5348  
AD5346 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
V
GH  
EF  
1
38  
37  
36  
35  
34  
33  
32  
31  
30  
PD  
REF  
V
2
CLR  
REF  
V
V
CD  
3
REF  
40 39 38 37 36 35 34 33 32 31  
GAIN  
WR  
4
V
V
V
V
V
A
B
C
D
1
2
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
DD  
AB  
A
OUT  
OUT  
OUT  
OUT  
RD  
CS  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
5
REF  
RD  
CS  
V
6
OUT  
8-BIT  
3
7
6
5
4
3
2
1
0
AD5346  
TOP VIEW  
(Not to Scale)  
V
V
V
B
C
D
7
DB  
7
OUT  
OUT  
OUT  
4
8-BIT  
8
DB  
6
5
4
5
AGND  
AGND  
AD5346  
TOP VIEW  
(Not to Scale)  
9
DB  
6
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
29 DB  
28  
AGND  
V
E
F
7
OUT  
DB  
V
E
F
3
2
1
0
OUT  
V
8
OUT  
27 DB  
V
OUT  
V
G
9
OUT  
DB  
DB  
26  
25  
V
G
OUT  
V
H
10  
OUT  
V
H
OUT  
11 12 13 14 15 16 17 18 19 20  
DGND  
BUF  
24 DGND  
23 DGND  
DGND  
DGND  
22  
21  
LDAC  
A0  
Figure 6. AD5346 Pin Configuration—LFCSP  
20 A2  
A1  
Figure 5. AD5346 Pin Configuration—TSSOP  
Table 5. AD5346 Pin Function Descriptions  
Pin Number  
TSSOP  
LFCSP  
35  
36  
37  
38, 39  
Mnemonic  
VREFGH  
VREFEF  
VREFCD  
VDD  
Function  
1
2
3
4
Reference Input for DACs G and H.  
Reference Input for DACs E and F.  
Reference Input for DACs C and D.  
Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled  
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP  
package must be at the same potential.  
5
40  
VREFAB  
Reference Input for DACs A and B.  
6–9,  
1–4,  
VOUTX  
Output of DAC X. Buffered output with rail-to-rail operation.  
11–14  
7–10  
10  
15,  
5, 6  
11,  
AGND  
DGND  
Analog Ground. Ground reference for analog circuitry.  
Digital Ground. Ground reference for digital circuitry.  
21–24  
17–20  
16  
17  
12  
13  
BUF  
LDAC  
Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.  
Active Low Control Input. Updates the DAC registers with the contents of the input registers, which  
allows all DAC outputs to be simultaneously updated.  
18  
19  
14  
15  
A0  
A1  
LSB Address Pin. Selects which DAC is to be written to.  
Address Pin. Selects which DAC is to be written to.  
20  
25–32  
33  
16  
21–28  
29  
A2  
DB0–DB7  
CS  
MSB Address Pin. Selects which DAC is to be written to.  
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.  
Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or  
with RD to read back data from a DAC.  
34  
35  
36  
37  
38  
30  
31  
32  
33  
34  
RD  
Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.  
Active Low Write Input. Used in conjunction with CS to write data to the parallel interface.  
Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.  
Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.  
Power-Down Pin. This active low control pin puts all DACs into power-down mode.  
WR  
GAIN  
CLR  
PD  
Rev. 0 | Page 7 of 24  
 
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