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AD5330BRUZ-REEL71 PDF预览

AD5330BRUZ-REEL71

更新时间: 2022-04-12 22:43:59
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 542K
描述
2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

AD5330BRUZ-REEL71 数据手册

 浏览型号AD5330BRUZ-REEL71的Datasheet PDF文件第1页浏览型号AD5330BRUZ-REEL71的Datasheet PDF文件第2页浏览型号AD5330BRUZ-REEL71的Datasheet PDF文件第4页浏览型号AD5330BRUZ-REEL71的Datasheet PDF文件第5页浏览型号AD5330BRUZ-REEL71的Datasheet PDF文件第6页浏览型号AD5330BRUZ-REEL71的Datasheet PDF文件第7页 
AD5330/AD5331/AD5340/AD5341  
SPECIFICATIONS  
VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.  
Table 1.  
B Version2  
Parameter1  
DC PERFORMANCE3, 4  
Min Typ  
Max  
Unit  
Conditions/Comments  
AD5330  
Resolution  
8
Bits  
LSB  
0.25 LSB  
Relative Accuracy  
Differential Nonlinearity  
AD533ꢀ  
0.ꢀ5  
0.02  
Guaranteed monotonic by design over all codes  
Guaranteed monotonic by design over all codes  
Guaranteed monotonic by design over all codes  
Resolution  
ꢀ0  
0.5  
0.05  
Bits  
LSB  
LSB  
Relative Accuracy  
Differential Nonlinearity  
AD5340/AD534ꢀ  
Resolution  
Relative Accuracy  
Differential Nonlinearity  
Offset Error  
4
0.5  
ꢀ2  
2
0.2  
0.4  
0.ꢀ5  
ꢀ0  
ꢀ0  
−ꢀ2  
−5  
−10  
Bits  
LSBs  
LSB  
% of FSR  
% of FSR  
mV  
ꢀ1  
3
10  
Gain Error  
Lower Deadband5  
Upper Deadband  
Offset Error Drift1  
Gain Error Drift1  
DC Power Supply Rejection Ratio1  
DAC REFERENCE INPUT1  
VREF Input Range  
Lower deadband exists only if offset error is negative  
VDD = 5 V; upper deadband exists only if VREF = VDD  
10  
mV  
ppm of FSR/°C  
ppm of FSR/°C  
dB  
ΔVDD = ꢀ0%  
0.25  
VDD  
VDD  
V
V
Buffered reference (AD5330, AD5340, and AD534ꢀ)  
Unbuffered reference  
VREF Input Impedance  
>ꢀ0  
ꢀ80  
90  
MΩ  
kΩ  
kΩ  
dB  
Buffered reference (AD5330, AD5340, and AD534ꢀ)  
Unbuffered reference; gain = ꢀ, input impedance = RDAC  
Unbuffered reference; gain = 2, input impedance = RDAC  
Frequency = ꢀ0 kHz  
Reference Feedthrough  
OUTPUT CHARACTERISTICS1  
Minimum Output Voltage4, 7  
Maximum Output Voltage4, 7  
DC Output Impedance  
−90  
0.00ꢀ  
VDD − 0.00ꢀ  
V min  
V max  
Ω
mA  
mA  
μs  
Rail-to-rail operation  
0.5  
25  
ꢀ5  
2.5  
5
Short-Circuit Current  
VDD = 5 V  
VDD = 3 V  
Power-Up Time  
Coming out of power-down mode; VDD = 5 V  
Coming out of power-down mode; VDD = 3 V  
μs  
LOGIC INPUTS1  
Input Current  
Input Low Voltage, VIL  
μA  
V
V
0.8  
0.1  
0.5  
VDD = 5 V ꢀ0%  
VDD = 3 V ꢀ0%  
VDD = 2.5 V  
V
Input High Voltage, VIH  
Pin Capacitance  
2.4  
2.ꢀ  
2.0  
V
V
V
pF  
VDD = 5 V ꢀ0%  
VDD = 3 V ꢀ0%  
VDD = 2.5 V  
3
Rev. A | Page 3 of 28  
 

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