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AD532SH/883B PDF预览

AD532SH/883B

更新时间: 2024-01-04 08:42:26
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
8页 182K
描述
Analog Multiplier/Divider

AD532SH/883B 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:, CAN10,.23Reach Compliance Code:unknown
风险等级:5.64模拟集成电路 - 其他类型:ANALOG MULTIPLIER OR DIVIDER
JESD-30 代码:O-MBCY-W10JESD-609代码:e0
标称负供电电压 (Vsup):-15 V端子数量:10
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:METAL封装等效代码:CAN10,.23
封装形状:ROUND封装形式:CYLINDRICAL
电源:+-15 V认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B子类别:Analog Computational Functions
最大供电电流 (Isup):12 mA标称供电电压 (Vsup):15 V
技术:BIPOLAR温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:WIRE
端子位置:BOTTOMBase Number Matches:1

AD532SH/883B 数据手册

 浏览型号AD532SH/883B的Datasheet PDF文件第2页浏览型号AD532SH/883B的Datasheet PDF文件第3页浏览型号AD532SH/883B的Datasheet PDF文件第4页浏览型号AD532SH/883B的Datasheet PDF文件第5页浏览型号AD532SH/883B的Datasheet PDF文件第6页浏览型号AD532SH/883B的Datasheet PDF文件第8页 
AD532  
SQUARE ROOT  
DIFFERENCE OF SQUARES  
Z
V
=
10VZ  
V
OUT  
X
Z
X
Y
1
2
Z
X
1
2
X
X
V
AD532  
V
OUT  
OUT  
AD532  
OUT  
OUT  
Y
Y
1
Y
Y
20kꢂ  
20kꢂ  
1
2
2
X
Y  
10V  
+V  
+V  
V  
S
V
=
2
S
OS  
+V  
V  
S
OUT  
2
S
Y  
1kꢂ  
(SF)  
10kꢂ  
(OPTIONAL)  
20kꢂ  
AD741KH  
47kꢂ  
2.2kꢂ  
10kꢂ  
V  
S
S
20kꢂ  
(X )  
0
Figure 15. Differential of Squares Connection  
+V  
V  
S
S
The differential input capability of the AD532 allows for the  
algebraic solution of several interesting functions, such as the  
difference of squares, X2 Y2/10 V. As shown in Figure 15, the  
AD532 is configured in the square mode, with a simple unity  
gain inverter connected between one of the signal inputs (Y)  
and one of the inverting input terminals (YIN) of the multiplier.  
The inverter should use precision (0.1%) resistors or be other-  
wise trimmed for unity gain for best accuracy.  
Figure 14. Square Rooter Connection  
The connections for square root mode are shown in Figure 14.  
Similar to the divide mode, the multiplier cell is connected in  
the feedback of the op amp by connecting the output back to  
both the X and Y inputs. The diode D1 is connected as shown  
to prevent latch-up as ZIN approaches 0 volts. In this case, the  
V
OS adjustment is made with ZIN = +0.1 V dc, adjusting VOS to  
obtain 1.0 V dc in the output, VOUT = ±10 V Z. For optimum  
performance, gain (S.F.) and offset (X0) adjustments are recom-  
mended as shown and explained in Table I.  
REV. C  
–7–  

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