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AD532SH/883B PDF预览

AD532SH/883B

更新时间: 2024-01-15 10:36:08
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
8页 182K
描述
Analog Multiplier/Divider

AD532SH/883B 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:, CAN10,.23Reach Compliance Code:unknown
风险等级:5.64模拟集成电路 - 其他类型:ANALOG MULTIPLIER OR DIVIDER
JESD-30 代码:O-MBCY-W10JESD-609代码:e0
标称负供电电压 (Vsup):-15 V端子数量:10
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:METAL封装等效代码:CAN10,.23
封装形状:ROUND封装形式:CYLINDRICAL
电源:+-15 V认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B子类别:Analog Computational Functions
最大供电电流 (Isup):12 mA标称供电电压 (Vsup):15 V
技术:BIPOLAR温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:WIRE
端子位置:BOTTOMBase Number Matches:1

AD532SH/883B 数据手册

 浏览型号AD532SH/883B的Datasheet PDF文件第2页浏览型号AD532SH/883B的Datasheet PDF文件第3页浏览型号AD532SH/883B的Datasheet PDF文件第4页浏览型号AD532SH/883B的Datasheet PDF文件第5页浏览型号AD532SH/883B的Datasheet PDF文件第6页浏览型号AD532SH/883B的Datasheet PDF文件第7页 
Internally Trimmed  
a
Integrated Circuit Multiplier  
AD532  
PIN CONFIGURATIONS  
FEATURES  
Pretrimmed to 1.0% (AD532K)  
Y
2
No External Components Required  
Guaranteed 1.0% max 4-Quadrant Error (AD532K)  
Diff Inputs for (X1 – X2) (Y1 – Y2)/10 V Transfer Function  
Monolithic Construction, Low Cost  
1
2
3
4
5
6
7
14 +V  
S
Z
V
OS  
Y
1
13  
12  
11  
10  
9
OUT  
Y
1
2
+V  
S
GND  
–V  
Y
S
AD532  
TOP VIEW  
(Not to Scale)  
AD532  
TOP VIEW  
(Not to Scale)  
NC  
NC  
NC  
V
OS  
APPLICATIONS  
Multiplication, Division, Squaring, Square Rooting  
Algebraic Computation  
Power Measurements  
Instrumentation Applications  
Available in Chip Form  
Z
X
2
GND  
X
2
X
8
X
1
NC  
OUT  
1
–V  
S
NC = NO CONNECT  
2
3
1
20 19  
18  
Y
4
5
6
7
8
–V  
2
S
17  
16  
NC  
V
NC  
NC  
NC  
AD532  
TOP VIEW  
(Not to Scale)  
OS  
15 NC  
14  
PRODUCT DESCRIPTION  
GND  
NC  
The AD532 is the first pretrimmed single chip monolithic multi-  
plier/divider. It guarantees a maximum multiplying error of  
±1.0% and a ±10 V output voltage without the need for any  
external trimming resistors or output op amp. Because the  
AD532 is internally trimmed, its simplicity of use provides design  
engineers with an attractive alternative to modular multipliers,  
and its monolithic construction provides significant advantages  
in size, reliability and economy. Further, the AD532 can be used  
as a direct replacement for other IC multipliers that require  
external trim networks.  
9
10 11 12 13  
NC = NO CONNECT  
GUARANTEED PERFORMANCE OVER TEMPERATURE  
The AD532J and AD532K are specified for maximum multiplying  
errors of ±2% and ±1% of full scale, respectively at 25°C, and  
are rated for operation from 0°C to 70°C. The AD532S has a  
maximum multiplying error of ±1% of full scale at 25°C; it is  
also 100% tested to guarantee a maximum error of ±4% at the  
extended operating temperature limits of –55°C and +125°C. All  
devices are available in either the hermetically-sealed TO-100  
metal can, TO-116 ceramic DIP or LCC packages. J, K, and  
S grade chips are also available.  
FLEXIBILITY OF OPERATION  
The AD532 multiplies in four quadrants with a transfer func-  
tion of (X1 – X2)(Y1 – Y2)/10 V, divides in two quadrants with  
a 10 V Z/(X1 – X2) transfer function, and square roots in one  
quadrant with a transfer function of ±± 10 V Z. In addition to  
these basic functions, the differential X and Y inputs provide  
significant operating flexibility both for algebraic computation and  
transducer instrumentation applications. Transfer functions,  
such as XY/10 V, (X2 – Y2)/10 V, ±X2/10 V, and 10 V Z/(X1 – X2),  
are easily attained and are extremely useful in many modulation  
and function generation applications, as well as in trigonometric  
calculations for airborne navigation and guidance applications,  
where the monolithic construction and small size of the AD532  
offer considerable system advantages. In addition, the high  
CMRR (75 dB) of the differential inputs makes the AD532  
especially well qualified for instrumentation applications, as it  
can provide an output signal that is the product of two transducer-  
generated input signals.  
ADVANTAGES OF ON-THE-CHIP TRIMMING OF THE  
MONOLITHIC AD532  
1. True ratiometric trim for improved power supply rejection.  
2. Reduced power requirements since no networks across sup-  
plies are required.  
3. More reliable since standard monolithic assembly techniques  
can be used rather than more complex hybrid approaches.  
4. High impedance X and Y inputs with negligible circuit loading.  
5. Differential X and Y inputs for noise rejection and additional  
computational flexibility.  
REV. C  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2001  

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