AD532JD+

更新时间： 2024-02-11 14:49:04

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
7页	139K
描述
Internally Trimmed Integrated Circuit Multiplier

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AD532JD+ 技术参数

Source Url Status Check Date：	2013-05-01 14:56:12.241	是否无铅：	含铅
是否Rohs认证：	不符合	生命周期：	Not Recommended
零件包装代码：	SMT	包装说明：	TO-100, CAN10,.23
针数：	10	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	7.53	模拟集成电路 - 其他类型：	ANALOG MULTIPLIER OR DIVIDER
标称带宽：	1 MHz	JESD-30 代码：	O-MBCY-W10
JESD-609代码：	e0	负电源电压最大值（Vsup）：	-22 V
负电源电压最小值（Vsup）：	-10 V	标称负供电电压 (Vsup)：	-15 V
最大负输入电压：	-10 V	功能数量：	1
端子数量：	10	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	METAL
封装代码：	TO-100	封装等效代码：	CAN10,.23
封装形状：	ROUND	封装形式：	CYLINDRICAL
峰值回流温度（摄氏度）：	NOT APPLICABLE	最大正输入电压：	10 V
电源：	+-15 V	认证状态：	Not Qualified
子类别：	Analog Computational Functions	最大供电电流 (Isup)：	6 mA
最大供电电压 (Vsup)：	22 V	最小供电电压 (Vsup)：	10 V
标称供电电压 (Vsup)：	15 V	表面贴装：	NO
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn63Pb37)
端子形式：	WIRE	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT APPLICABLE	Base Number Matches：	1

AD532JD+ 数据手册

AD532

DYNAMIC CHARACTERISTICS

NOISE CHARACTERISTICS

The closed loop frequency response of the AD532 in the multi-

plier mode typically exhibits a 3 dB bandwidth of 1 MHz and

rolls off at 6 dB/octave thereafter. Response through all inputs is

essentially the same as shown in Figure 7. In the divide mode,

the closed loop frequency response is a function of the absolute

value of the denominator voltage as shown in Figure 8.

All AD532s are screened on a sampling basis to assure that

output noise will have no appreciable effect on accuracy. Typi-

cal spot noise vs. frequency is shown in Figure 10.

Stable operation is maintained with capacitive loads to 1000 pF

in all modes, except the square root for which 50 pF is a safe

upper limit. Higher capacitive loads can be driven if a 100 Ω

resistor is connected in series with the output for isolation.

Figure 10. Spot Noise vs. Frequency

APPLICATIONS CONSIDERATIONS

The performance and ease of use of the AD532 is achieved

through the laser trimming of thin-film resistors deposited di-

rectly on the monolithic chip. This trimming-on-the-chip tech-

nique provides a number of significant advantages in terms of

cost, reliability and flexibility over conventional in-package

trimming of off-the-chip resistors mounted or deposited on a

hybrid substrate.

Figure 8. Frequency Response, Dividing

First and foremost, trimming on the chip eliminates the need

for a hybrid substrate and the additional bonding wires that are

required between the resistors and the multiplier chip. By trim-

ming more appropriate resistors on the AD532 chip itself, the

second input terminals that were once committed to external

trimming networks (e.g., AD530) have been freed to allow fully

differential operation at both the X and Y inputs. Further, the

requirement for an input attenuator to adjust the gain at the Y

input has been eliminated, letting the user take full advantage of

the high input impedance properties of the input differential

amplifiers. Thus, the AD532 offers greater flexibility for both

algebraic computation and transducer instrumentation

applications.

POWER SUPPLY CONSIDERATIONS

Although the AD532 is tested and specified with ±15 V dc

supplies, it may be operated at any supply voltage from ±10 V

to ±18 V for the J and K versions, and ±10 V to ±22 V for the S

version. The input and output signals must be reduced propor-

tionately to prevent saturation; however, with supply voltages

below ±15 V, as shown in Figure 9. Since power supply sensitiv-

ity is not dependent on external null networks as in the AD530

and other conventionally nulled multipliers, the power supply

rejection ratios are improved from 3 to 40 times in the AD532.

Finally, provision for fine trimming the output voltage offset has

been included. This connection is optional, however, as the

AD532 has been factory-trimmed for total performance as

described in the listed specifications.

REPLACING OTHER IC MULTIPLIERS

Existing designs using IC multipliers that require external trim-

ming networks (such as the AD530) can be simplified using the

pin-for-pin replaceability of the AD532 by merely grounding

the X₂, Y₂and V_OSterminals. (The V_OSterminal should always

be grounded when unused.)

Figure 9. Signal Swing vs. Supply

REV. B

–5–

1 2 3 456 7

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与AD532JD+相关器件

型号	品牌	描述	获取价格	数据表
AD532JDZ	ADI	Internally Trimmed Integrated Circuit Multiplier	获取价格
AD532JH	ADI	Internally Trimmed Integrated Circuit Multiplier	获取价格
AD532JH/+	ADI	AD532JH/+	获取价格
AD532JHZ	ADI	Internally Trimmed Integrated Circuit Multiplier	获取价格
AD532K	ADI	Internally Trimmed Integrated Circuit Multiplier	获取价格
AD532KCHIPS	ADI	AD532KCHIPS	获取价格

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