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AD532JCHIP PDF预览

AD532JCHIP

更新时间: 2024-02-03 06:08:35
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
7页 139K
描述
Internally Trimmed Integrated Circuit Multiplier

AD532JCHIP 技术参数

Source Url Status Check Date:2013-05-01 14:56:12.241是否无铅: 含铅
是否Rohs认证: 不符合生命周期:Not Recommended
零件包装代码:SMT包装说明:TO-100, CAN10,.23
针数:10Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:7.53模拟集成电路 - 其他类型:ANALOG MULTIPLIER OR DIVIDER
标称带宽:1 MHzJESD-30 代码:O-MBCY-W10
JESD-609代码:e0负电源电压最大值(Vsup):-22 V
负电源电压最小值(Vsup):-10 V标称负供电电压 (Vsup):-15 V
最大负输入电压:-10 V功能数量:1
端子数量:10最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:METAL
封装代码:TO-100封装等效代码:CAN10,.23
封装形状:ROUND封装形式:CYLINDRICAL
峰值回流温度(摄氏度):NOT APPLICABLE最大正输入电压:10 V
电源:+-15 V认证状态:Not Qualified
子类别:Analog Computational Functions最大供电电流 (Isup):6 mA
最大供电电压 (Vsup):22 V最小供电电压 (Vsup):10 V
标称供电电压 (Vsup):15 V表面贴装:NO
温度等级:MILITARY端子面层:Tin/Lead (Sn63Pb37)
端子形式:WIRE端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT APPLICABLEBase Number Matches:1

AD532JCHIP 数据手册

 浏览型号AD532JCHIP的Datasheet PDF文件第1页浏览型号AD532JCHIP的Datasheet PDF文件第2页浏览型号AD532JCHIP的Datasheet PDF文件第4页浏览型号AD532JCHIP的Datasheet PDF文件第5页浏览型号AD532JCHIP的Datasheet PDF文件第6页浏览型号AD532JCHIP的Datasheet PDF文件第7页 
AD532  
ORDERING GUIDE  
CHIP DIMENSIONS AND BONDING DIAGRAM  
Contact factory for latest dimensions.  
Temperature  
Ranges  
Package  
Descriptions  
Package  
Options  
Dimensions shown in inches and (mm).  
Model  
AD532JD  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
–55°C to +125°C  
–55°C to +125°C  
Side Brazed DIP  
Side Brazed DIP  
Side Brazed DIP  
Side Brazed DIP  
Header  
Header  
Chip  
Side Brazed DIP  
Side Brazed DIP  
Side Brazed DIP  
LCC  
Header  
Header  
D-14  
D-14  
D-14  
D-14  
H-10A  
H-10A  
AD532JD/+  
AD532KD  
AD532KD/+  
AD532JH  
AD532KH  
AD532J Chip  
AD532SD  
AD532SD/883B  
JM38510/13903BCA –55°C to +125°C  
AD532SE/883B  
AD532SH  
AD532SH/883B  
D-14  
D-14  
D-14  
E-20A  
H-10A  
H-10A  
H-10A  
–55°C to +125°C  
–55°C to +125°C  
–55°C to +125°C  
JM38510/13903BIA –55°C to +125°C  
AD532S Chip –55°C to +125°C  
Header  
Chip  
FUNCTIONAL DESCRIPTION  
The functional block diagram for the AD532 is shown in Figure  
1, and the complete schematic in Figure 2. In the multiplying  
and squaring modes, Z is connected to the output to close the  
feedback around the output op amp. (In the divide mode, it is  
used as an input terminal.)  
The X and Y inputs are fed to high impedance differential am-  
plifiers featuring low distortion and good common-mode rejec-  
tion. The amplifier voltage offsets are actively laser trimmed  
to zero during production. The product of the two inputs is  
resolved in the multiplier cell using Gilbert’s linearized trans-  
conductance technique. The cell is laser trimmed to obtain  
VOUT = (X1 – X2)(Y1 – Y2)/10 volts. The built-in op amp is used  
to obtain low output impedance and make possible self-contained  
operation. The residual output voltage offset can be zeroed at  
VOS in critical applications . . . otherwise the VOS pin should be  
grounded.  
Figure 1. Functional Block Diagram  
Figure 2. Schematic Diagram  
–3–  
REV. B  

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