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AD5328ARU-REEL7

更新时间： 2024-02-25 17:45:35
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器光电二极管
页数 文件大小 规格书
28页 408K
描述
2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

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AD5328ARU-REEL7 技术参数

Source Url Status Check Date：2013-05-01 14:56:12.194是否无铅： 含铅
是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP16,.25
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.34Is Samacsys：N
最大模拟输出电压：5.499 V最小模拟输出电压：0.001 V
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：SERIALJESD-30 代码：R-PDSO-G16
JESD-609代码：e0长度：5 mm
最大线性误差 (EL)：0.3906%湿度敏感等级：1
位数：12功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：240电源：3/5 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大稳定时间：10 µs标称安定时间 (tstl)：8 µs
子类别：Other Converters最大压摆率：1.8 mA
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：20宽度：4.4 mm
Base Number Matches：1

AD5328ARU-REEL7 数据手册

 浏览型号AD5328ARU-REEL7的Datasheet PDF文件第5页浏览型号AD5328ARU-REEL7的Datasheet PDF文件第6页浏览型号AD5328ARU-REEL7的Datasheet PDF文件第7页浏览型号AD5328ARU-REEL7的Datasheet PDF文件第9页浏览型号AD5328ARU-REEL7的Datasheet PDF文件第10页浏览型号AD5328ARU-REEL7的Datasheet PDF文件第11页 
AD5308/AD5318/AD5328  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
LDAC  
SYNC  
SCLK  
DIN  
AD5308/  
AD5318/  
AD5328  
V
GND  
DD  
V
V
V
V
A
B
C
D
V
V
V
V
V
H
G
F
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
TOP VIEW  
(Not to Scale)  
E
V
ABCD  
EFGH  
REF  
REF  
Figure 3. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin No. Mnemonic Description  
1
LDAC  
This active low control input transfers the contents of the input registers to their respective DAC registers. Pulsing  
this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simul-  
taneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low.  
2
SYNC  
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it  
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges  
of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an  
interrupt and the write sequence is ignored by the device.  
3
VDD  
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF  
capacitor in parallel with a 0.1 μF capacitor to GND.  
4
5
6
7
8
VOUT  
VOUT  
VOUT  
VOUT  
A
B
C
D
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.  
Reference Input Pin for DACs A, B, C, and D. It can be configured as a buffered, unbuffered, or VDD input to the four  
DACs, depending on the state of the BUF and VDD control bits. It has an input range from 0.25 V to VDD in unbuffered  
mode and from 1 V to VDD in buffered mode.  
VREFABCD  
9
VREFEFGH  
Reference Input Pin for DACs E, F, G, and H. It can be configured as a buffered, unbuffered, or VDD input to the four  
DACs, depending on the state of the BUF and VDD control bits. It has an input range from 0.25 V to VDD in unbuffered  
mode and from 1 V to VDD in buffered mode.  
10  
11  
12  
13  
14  
15  
VOUT  
VOUT  
VOUT  
VOUT  
GND  
DIN  
E
F
G
H
Buffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.  
Ground Reference Point for All Circuitry on the Part.  
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the  
serial clock input. The DIN input buffer is powered down after each write cycle.  
16  
SCLK  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can  
be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.  
Rev. F | Page 8 of 28  
 
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AD5328ARU-REEL7 替代型号

型号 品牌 替代类型 描述 数据表
AD5328BRUZ ADI

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 		2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5328ARUZ ADI

功能相似

 		2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

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