AD5308/AD5318/AD5328
If the user wishes to update the DAC through software, the LDAC
pin should be tied high and the LDAC mode bits set as required.
Alternatively, if the user wishes to control the DAC through
hardware, i.e., the LDAC pin, the LDAC mode bits should be
set to LDAC high (default mode).
The bias generator, the output amplifiers, the resistor string,
and all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. In fact, it is pos-
sible to load new data to the input registers and DAC registers
during power-down. The DAC outputs will update as soon as
the device comes out of power-down mode. The time to exit
power-down is typically 2.5 µs for VDD = 5 V and 5 µs when
VDD = 3 V.
Use of the LDAC function enables double-buffering of the DAC
data, and the GAIN, BUF and VDD bits. There are two ways in
which the LDAC function can operate:
Synchronous LDAC: The DAC registers are updated after
new data is read in on the falling edge of the 16th SCLK pulse.
LDAC can be permanently low or pulsed as in Figure 1.
AMPLIFIER
RESISTOR-
STRING DAC
V
OUT
Asynchronous LDAC: The outputs are not updated at the
same time that the input registers are written to. When LDAC
goes low, the DAC registers are updated with the contents of
the input register.
POWER-DOWN
CIRCUITRY
Figure 10. Output Stage during Power-Down
DOUBLE-BUFFERED INTERFACE
MICROPROCESSOR INTERFACING
The AD5308/AD5318/AD5328 DACs all have double-buffered
interfaces consisting of two banks of registers: input and DAC.
The input registers are connected directly to the input shift
register, and the digital code is transferred to the relevant input
register on completion of a valid write sequence. The DAC
registers contain the digital code used by the resistor strings.
ADSP-2101/ADSP-2103 to AD5308/AD5318/AD5328 Interface
Figure 11 shows a serial interface between the AD5308/AD5318/
AD5328 and the ADSP-2101/ADSP-2103. The ADSP-2101/
ADSP-2103 should be set up to operate in the SPORT transmit
alternate framing mode. The ADSP-2101/ADSP-2103 SPORT
is programmed through the SPORT control register and should
be configured as follows: internal clock operation, active-low
framing, and 16-bit word length. Transmission is initiated by
writing a word to the Tx register after the SPORT has been
enabled. The data is clocked out on each rising edge of the
DSP’s serial clock and clocked into the AD5308/AD5318/
AD5328 on the falling edge of the DAC’s SCLK.
When the LDAC pin is high and the LDAC bits are set to (01),
the DAC registers are latched and the input registers may change
state without affecting the contents of the DAC registers. How-
ever, when the LDAC bits are set to (00) or when the LDAC
pin is brought low, the DAC registers become transparent and
the contents of the input registers are transferred to them.
The double-buffered interface is useful if the user requires simulta-
neous updating of all DAC outputs. The user may write to seven
of the input registers individually and then, by bringing LDAC
low when writing to the remaining DAC input register, all out-
puts will update simultaneously.
AD5308/
AD5318/
AD5328*
ADSP-2101/
ADSP-2103*
SYNC
TFS
These parts contain an extra feature whereby a DAC register is
not updated unless its input register has been updated since the
last time LDAC was low. Normally, when LDAC is brought
low, the DAC registers are filled with the contents of the input
registers. In the case of the AD5308/AD5318/AD5328, the part
will update the DAC register only if the input register has been
changed since the last time the DAC register was updated, thereby
removing unnecessary digital crosstalk.
DIN
DT
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. ADSP-2101/ADSP-2103 to AD5308
AD5318/AD5328 Interface
68HC11/68L11 to AD5308/AD5318/AD5328 Interface
Figure 12 shows a serial interface between the AD5308/AD5318/
AD5328 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5308/AD5318/
AD5328, while the MOSI output drives the serial data line
(DIN) of the DAC. The SYNC signal is derived from a port
line (PC7). The setup conditions for the correct operation of
this interface are as follows: the 68HC11/68L11 should be
configured so that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is being transmitted to the DAC, the SYNC line is
taken low (PC7). When the 68HC11/68L11 is configured as
above, data appearing on the MOSI output is valid on the falling
edge of SCK. Serial data from the 68HC11/68L11 is transmit-
ted in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle. Data is transmitted MSB first. To load data
to the AD5308/AD5318/AD5328, PC7 is left low after the first
eight bits are transferred, and a second serial write operation is
performed to the DAC. PC7 is taken high at the end of this
procedure.
POWER-DOWN MODE
The AD5308/AD5318/AD5328 have low power consumption,
typically dissipating 2.4 mW with a 3 V supply and 5 mW with a
5 V supply. Power consumption can be further reduced when the
DACs are not in use by putting them into power-down mode,
which was described previously.
When in default mode, all DACs work normally with a typical
power consumption of 1 mA at 5 V (800 µA at 3 V). However,
when all DACs are powered down, i.e., in power-down mode,
the supply current falls to 400 nA at 5 V (120 nA at 3 V). Not
only does the supply current drop, but the output stage is also
internally switched from the output of the amplifier, making it
open-circuit. This has the advantage that the output is three-
state while the part is in power-down mode, and provides a defined
input condition for whatever is connected to the output of the
DAC amplifier. The output stage is illustrated in Figure 10.
–14–
REV. B
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