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AD5327BRUZ-REEL

更新时间： 2024-01-12 00:12:34
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 585K
描述
2.5 V to 5.5 V, 400 muA, Quad Voltage Output

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中文翻译

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AD5327BRUZ-REEL 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1
最大模拟输出电压：5.499 V最小模拟输出电压：0.001 V
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：SERIALJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：5 mm
最大线性误差 (EL)：0.2441%湿度敏感等级：1
位数：12功能数量：1
端子数量：16最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大稳定时间：10 µs标称安定时间 (tstl)：8 µs
子类别：Other Converters最大压摆率：0.9 mA
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：4.4 mm

AD5327BRUZ-REEL 数据手册

 浏览型号AD5327BRUZ-REEL的Datasheet PDF文件第5页浏览型号AD5327BRUZ-REEL的Datasheet PDF文件第6页浏览型号AD5327BRUZ-REEL的Datasheet PDF文件第7页浏览型号AD5327BRUZ-REEL的Datasheet PDF文件第9页浏览型号AD5327BRUZ-REEL的Datasheet PDF文件第10页浏览型号AD5327BRUZ-REEL的Datasheet PDF文件第11页 
AD5307/AD5317/AD5327  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
1
2
3
4
5
6
7
8
16  
SDO  
CLR  
SYNC  
15  
LDAC  
AD5307/  
AD5317/ 14 SCLK  
AD5327  
V
DD  
13  
12  
11  
10  
9
DIN  
V
V
V
A
B
C
OUT  
OUT  
OUT  
TOP VIEW  
(Not to Scale)  
GND  
V
D
OUT  
V
AB  
CD  
PD  
REF  
DCEN  
V
REF  
Figure 5. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin  
No.  
Mnemonic Description  
1
CLR  
Active Low Control Input. Loads all 0s to all input and DAC registers. Therefore, the outputs also go to 0 V.  
2
LDAC  
Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this  
pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous  
update of all DAC outputs. Alternatively, this pin can be tied permanently low.  
3
VDD  
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF  
capacitor in parallel with a 0.1 μF capacitor to GND.  
4
5
6
7
VOUT  
VOUT  
VOUT  
A
B
C
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.  
Reference Input Pin for DAC A and DAC B. It can be configured as a buffered or unbuffered input to each or both of  
the DACs, depending on the state of the BUF bits in the serial input words to DAC A and DAC B. It has an input range  
of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.  
VREFAB  
8
VREFCD  
Reference Input Pin for DAC C and DAC D. It can be configured as a buffered or unbuffered input to each or both of  
the DACs, depending on the state of the BUF bits in the serial input words to DAC C and DAC D. It has an input range  
of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.  
9
DCEN  
PD  
Enables the Daisy-Chaining Option. It should be tied high if the part is being used in a daisy chain, and tied low if it is  
being used in standalone mode.  
Active Low Control Input. It acts like a hardware power-down option. All DACs go into power-down mode when this  
pin is tied low. The DAC outputs go into a high impedance state, and the current consumption of the part drops to  
300 nA @ 5 V (90 nA @ 3 V).  
10  
11  
12  
13  
VOUT  
GND  
DIN  
D
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.  
Ground Reference Point for All Circuitry on the Part.  
Serial Data Input. These devices each have a 16-bit shift register. Data is clocked into the register on the falling edge of  
the serial clock input. The DIN input buffer is powered down after each write cycle.  
14  
15  
SCLK  
SYNC  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be  
transferred at rates of up to 30 MHz. The SCLK input buffer is powered down after each write cycle.  
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers  
on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the  
following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and  
the write sequence is ignored by the device.  
16  
SDO  
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in  
the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the  
falling edge of the clock.  
Rev. C | Page 8 of 28  
 
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中文翻译

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AD5327BRUZ-REEL 替代型号

型号 品牌 替代类型 描述 数据表
AD5316ARUZ ADI

类似代替

 		2.5 V to 5.5 V, 400 µA, 2-Wire Interface Quad Voltage Output 10-Bit DAC
AD5327BRUZ ADI

类似代替

 		2.5 V to 5.5 V, 400 muA, Quad Voltage Output

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