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AD5321BRTZ-REEL PDF预览

AD5321BRTZ-REEL

更新时间: 2024-01-24 04:42:04
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 565K
描述
SERIAL INPUT LOADING, 8us SETTLING TIME, 12-BIT DAC, PDSO6, ROHS COMPLIANT, MO-178AB, SOT-23, 6 PIN

AD5321BRTZ-REEL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:LSSOP, TSOP6,.11,37针数:6
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.36
最大模拟输出电压:5.499 V最小模拟输出电压:0.001 V
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:R-PDSO-G6
JESD-609代码:e4长度:2.9 mm
最大线性误差 (EL):0.3906%湿度敏感等级:1
位数:12功能数量:1
端子数量:6最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装等效代码:TSOP6,.11,37
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3/5 V
认证状态:Not Qualified座面最大高度:1.45 mm
最大稳定时间:10 µs标称安定时间 (tstl):8 µs
子类别:Other Converters最大压摆率:0.225 mA
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:1.6 mm
Base Number Matches:1

AD5321BRTZ-REEL 数据手册

 浏览型号AD5321BRTZ-REEL的Datasheet PDF文件第5页浏览型号AD5321BRTZ-REEL的Datasheet PDF文件第6页浏览型号AD5321BRTZ-REEL的Datasheet PDF文件第7页浏览型号AD5321BRTZ-REEL的Datasheet PDF文件第9页浏览型号AD5321BRTZ-REEL的Datasheet PDF文件第10页浏览型号AD5321BRTZ-REEL的Datasheet PDF文件第11页 
AD5305/AD5315/AD5325  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
V
1
2
3
4
5
10  
DD  
A0  
AD5305/  
AD5315/  
AD5325  
TOP VIEW  
(Not to Scale)  
9
SCL  
SDA  
GND  
V
V
V
A
B
C
OUT  
OUT  
OUT  
8
7
6
V
D
REFIN  
OUT  
Figure 3. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin No. Mnemonic Description  
1
2
3
4
5
6
7
8
VDD  
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND.  
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.  
Reference Input Pin for All Four DACs. It has an input range from 0.25 V to VDD.  
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.  
Ground Reference Point for All Circuitry on the Part.  
VOUT  
VOUT  
VOUT  
REFIN  
VOUT  
A
B
C
D
GND  
SDA  
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift  
register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up  
resistor.  
9
SCL  
A0  
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift  
register. Clock rates of up to 400 kb/s can be accommodated in the 2-wire interface.  
Address Input. Sets the least significant bit of the 7-bit slave address.  
10  
Rev. G | Page 8 of 24  
 

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