AD5321BRT

更新时间： 2024-01-31 05:32:51

品牌	Logo	应用领域
亚德诺 - ADI		转换器数模转换器光电二极管
页数	文件大小	规格书
15页	181K
描述
+2.5 V to +5.5 V, 120 uA, 2-Wire Interface, Voltage Output 8-/10-/12-Bit DACs

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技术参数
数据手册
替代型号

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AD5321BRT 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	LSSOP, TSOP6,.11,37	针数：	6
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.36
最大模拟输出电压：	5.499 V	最小模拟输出电压：	0.001 V
转换器类型：	D/A CONVERTER	输入位码：	BINARY
输入格式：	SERIAL	JESD-30 代码：	R-PDSO-G6
JESD-609代码：	e4	长度：	2.9 mm
最大线性误差 (EL)：	0.3906%	湿度敏感等级：	1
位数：	12	功能数量：	1
端子数量：	6	最高工作温度：	105 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LSSOP	封装等效代码：	TSOP6,.11,37
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	3/5 V
认证状态：	Not Qualified	座面最大高度：	1.45 mm
最大稳定时间：	10 µs	标称安定时间 (tstl)：	8 µs
子类别：	Other Converters	最大压摆率：	0.225 mA
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	0.95 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	1.6 mm
Base Number Matches：	1

AD5321BRT 数据手册

AD5301/AD5311/AD5321

3. When all data bits have been read or written, a STOP condi-

tion is established by the master. A STOP condition is de-

fined as a low-to-high transition on the SDA line while SCL

is high. In Write mode, the master will pull the SDA line

high during the 10th clock pulse to establish a STOP condi-

tion. In Read mode, the master will issue a No Acknowledge

for the 9th clock pulse (i.e., the SDA line remains high). The

master will then bring the SDA line low before the 10th clock

pulse and then high during the 10th clock pulse to establish a

STOP condition.

SERIAL INTERFACE

2-WIRE SERIAL BUS

The AD5301/AD5311/AD5321 are controlled via an I²C-

compatible serial bus. The DACs are connected to this bus as

slave devices (no clock is generated by the AD5301/AD5311/

AD5321 DACs).

The AD5301/AD5311/AD5321 has a 7-bit slave address. In the

case of the 6-pin device, the 6 MSBs are 000110 and the LSB is

determined by the state of the A0 pin. In the case of the 8-pin

device, the 5 MSBs are 00011 and the 2 LSBs are determined

by the state of the A0 and A1 pins. A1 and A0 allow the user to

use up to four of these DACs on one bus.

In the case of the AD5301/AD5311/AD5321, a write operation

contains two bytes whereas a read operation may contain one or

two bytes. See Figures 24 to 29 below for a graphical explana-

tion of the serial interface.

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START

condition, which is when a high to low transition on the SDA

line occurs while SCL is high. The following byte is the ad-

dress byte which consists of the 7-bit slave address followed

by an R/W bit (this bit determines whether data will be read

from or written to the slave device).

A repeated write function gives the user flexibility to update the

DAC output a number of times after addressing the part only

once. During the write cycle, each multiple of two data bytes

will update the DAC output. For example, after the DAC has

acknowledged its address byte, and receives two data bytes, the

DAC output will update after the two data bytes, if another two

data bytes are written to the DAC while it is still the addressed

slave device, these data bytes will also cause an output update.

Repeat read of the DAC is also allowed.

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is termed the Acknowledge bit). At

this stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from its

serial register. If the R/W bit is high, the master will read

from the slave device. However, if the R/W bit is low, the

master will write to the slave device.

INPUT SHIFT REGISTER

The input shift register is 16 bits wide. Figure 23 illustrates the

contents of the input shift register for each part. Data is loaded

into the device as a 16-bit word under the control of a serial

clock input, SCL. The timing diagram for this operation is

shown in Figure 1. The 16-bit word consists of four control bits

followed by 8, 10 or 12 bits of data, depending on the device

type. MSB (Bit 15) is loaded first. The first two bits are “don’t

cares.” The next two are control bits that control the mode of

operation of the device (normal mode or any one of three

power-down modes). See Power Down Modes section for a

complete description. The remaining bits are left-justified DAC

data bits, starting with the MSB and ending with the LSB.

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an Acknowledge

bit). The transitions on the SDA line must occur during the

low period of SCL and remain stable during the high period

of SCL.

DB15 (MSB)

DB0 (LSB)

PD1 PD0 D7

DATA BITS

Figure 23a. AD5301 Input Shift Register Contents

DB15 (MSB)

DB0 (LSB)

PD1 PD0 D9

DATA BITS

Figure 23b. AD5311 Input Shift Register Contents

DB15 (MSB)

DB0 (LSB)

D1 D0

PD1 PD0 D11 D10 D9

DATA BITS

Figure 23c. AD5321 Input Shift Register Contents

–10–

REV. 0

1...7 8 91011 12 13...15

中文翻译

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AD5321BRT 替代型号

型号	品牌	替代类型	描述	数据表
AD5321BRTZ-REEL	ADI	功能相似	SERIAL INPUT LOADING, 8us SETTLING TIME, 12-BIT DAC, PDSO6, ROHS COMPLIANT, MO-178AB, SOT-
AD5321BRT-500RL7	ADI	功能相似	2.5 V to 5.5 V, 120 Î¼A, 2-Wire Interface, Vo

与AD5321BRT相关器件

型号	品牌	描述	获取价格	数据表
AD5321BRT-500RL7	ADI	2.5 V to 5.5 V, 120 Î¼A, 2-Wire Interface, Vo	获取价格
AD5321BRT-REEL	ADI	2.5 V to 5.5 V, 120 Î¼A, 2-Wire Interface, Vo	获取价格
AD5321BRT-REEL7	ADI	2.5 V to 5.5 V, 120 Î¼A, 2-Wire Interface, Vo	获取价格
AD5321BRTZ-500RL7	ROCHESTER	SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO6, ROHS COMPLIANT, MO-178AB, SOT	获取价格
AD5321BRTZ-500RL71	ADI	2.5 V to 5.5 V, 120 Î¼A, 2-Wire Interface, Vo	获取价格
AD5321BRTZ-REEL	ADI	SERIAL INPUT LOADING, 8us SETTLING TIME, 12-BIT DAC, PDSO6, ROHS COMPLIANT, MO-178AB, SOT-	获取价格

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