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AD5305BRMZ

更新时间： 2024-01-30 17:13:47
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器光电二极管PC
页数 文件大小 规格书
24页 565K
描述
2.5 V to 5.5 V, 500 muA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs

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AD5305BRMZ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：10
Reach Compliance Code：unknown风险等级：5.35
最大模拟输出电压：5.499 V最小模拟输出电压：0.001 V
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：SERIALJESD-30 代码：S-PDSO-G10
JESD-609代码：e3长度：3 mm
最大线性误差 (EL)：0.2441%湿度敏感等级：1
位数：8功能数量：1
端子数量：10最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：SQUARE
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：COMMERCIAL座面最大高度：1.1 mm
标称安定时间 (tstl)：6 µs标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3 mmBase Number Matches：1

AD5305BRMZ 数据手册

 浏览型号AD5305BRMZ的Datasheet PDF文件第15页浏览型号AD5305BRMZ的Datasheet PDF文件第16页浏览型号AD5305BRMZ的Datasheet PDF文件第17页浏览型号AD5305BRMZ的Datasheet PDF文件第19页浏览型号AD5305BRMZ的Datasheet PDF文件第20页浏览型号AD5305BRMZ的Datasheet PDF文件第21页 
AD5305/AD5315/AD5325  
SCL  
0
0
0
1
1
0
A0  
R/W  
X
X
LSB  
SDA  
START  
COND  
BY  
ACK  
BY  
AD53x5  
MSB  
ACK  
BY  
AD53x5  
ADDRESS BYTE  
POINTER BYTE  
MASTER  
SCL  
SDA  
MSB  
LSB  
0
0
0
1
1
0
A0  
R/W  
REPEATED  
START  
COND  
ACK  
BY  
AD53x5  
ACK  
BY  
MASTER  
ADDRESS BYTE  
DATA BYTE  
BY  
MASTER  
SCL  
SDA  
MSB  
LSB  
NO  
ACK  
BY  
STOP  
COND  
BY  
LEAST SIGNIFICANT DATA BYTE  
MASTER  
MASTER  
NOTE: DATA BYTES ARE THE SAME AS THOSE IN THE WRITE SEQUENCE EXCEPT THAT DON’T CARES ARE READ BACK AS 0s.  
Figure 34. Readback Sequence  
These parts contain an extra feature whereby the DAC register  
is not updated unless its input register has been updated since  
DOUBꢀE-BUFFERED INTERFACE  
The AD5305/AD5315/AD5325 DACs have double-buffered  
interfaces consisting of two banks of registers—input registers  
and DAC registers. The input register is directly connected to the  
input shift register and the digital code is transferred to the relevant  
input register on completion of a valid write sequence. The DAC  
register contains the digital code used by the resistor string.  
LDAC  
the last time that  
was brought low. Normally, when  
LDAC  
is brought low, the DAC registers are filled with the  
contents of the input registers. In the case of the AD5305/AD5315/  
AD5325, the part updates the DAC register only if the input  
register has been changed since the last time the DAC register  
was updated, thereby removing unnecessary digital crosstalk.  
LDAC  
Access to the DAC register is controlled by the  
bit. When  
bit is set high, the DAC register is latched and,  
therefore, the input register can change state without affecting  
LDAC  
POWER-DOWN MODES  
LDAC  
the  
The AD5305/AD5315/AD5325 have very low power consumption,  
dissipating typically 1.5 mW with a 3 V supply and 3 mW with  
a 5 V supply. Power consumption can be further reduced when  
the DACs are not in use by putting them into one of three  
power-down modes, which are selected by Bit 15 and Bit 14  
(PD1 and PD0) of the data byte. Table 8 shows how the state of  
the bits corresponds to the mode of operation of the DAC.  
the contents of the DAC register. However, when the  
bit  
is set low, the DAC register becomes transparent and the  
contents of the input register are transferred to it.  
This is useful if the user requires simultaneous updating of all  
DAC outputs. The user can write to three of the input registers  
LDAC  
individually and then, by setting the  
bit low when  
Table 8. PD1/PD0 Operating Modes  
writing to the remaining DAC input register, all outputs update  
simultaneously.  
PD1  
PD0  
Operating Mode  
0
0
1
1
0
1
0
1
Normal Operation  
Power-Down (1 kΩ load to GND)  
Power-Down (100 kΩ load to GND)  
Power-Down (three-state output)  
Rev. G | Page 18 of 24  
 
 
 
 
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