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AD5300BRTZ-REEL PDF预览

AD5300BRTZ-REEL

更新时间: 2024-02-23 04:39:35
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
12页 202K
描述
+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23

AD5300BRTZ-REEL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:LSSOP, TSOP6,.11,37针数:6
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.31
最大模拟输出电压:5.5 V最小模拟输出电压:
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:R-PDSO-G6
JESD-609代码:e3长度:2.9 mm
最大线性误差 (EL):0.3906%湿度敏感等级:1
位数:8功能数量:1
端子数量:6最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装等效代码:TSOP6,.11,37
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3/5 V
认证状态:Not Qualified座面最大高度:1.45 mm
最大稳定时间:6 µs标称安定时间 (tstl):4 µs
子类别:Other Converters最大压摆率:0.25 mA
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:1.6 mm
Base Number Matches:1

AD5300BRTZ-REEL 数据手册

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AD5300  
PIN CONFIGURATIONS  
MSOP  
SOT-23  
1
2
3
1
8
7
6
5
V
GND  
DIN  
6
5
4
SYNC  
SCLK  
DIN  
V
OUT  
DD  
AD5300  
TOP VIEW  
(Not to Scale)  
2
3
4
GND  
NC  
NC  
AD5300  
TOP VIEW  
(Not to Scale)  
V
SCLK  
SYNC  
DD  
V
OUT  
NC = NO CONNECT  
PIN FUNCTION DESCRIPTIONS  
SOT-23 MSOP  
Pin No. Pin No. Mnemonic  
Function  
1
2
3
4
8
1
VOUT  
GND  
VDD  
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.  
Ground Reference Point for All Circuitry on the Part.  
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and VDD should be decoupled  
to GND.  
4
5
6
7
6
5
DIN  
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the  
falling edge of the serial clock input.  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial  
clock input. Data can be transferred at rates up to 30 MHz.  
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the  
input data. When SYNC goes low, it enables the input shift register and data is transferred in on the  
falling edges of the following clocks. The DAC is updated following the 16th clock cycle, unless  
SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and  
the write sequence is ignored by the DAC.  
SCLK  
SYNC  
NC  
2, 3  
NC  
No Connect.  
REV. C  
–4–  

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