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AD5300BCHIPS PDF预览

AD5300BCHIPS

更新时间: 2024-01-24 06:08:15
品牌 Logo 应用领域
亚德诺 - ADI 输入元件转换器
页数 文件大小 规格书
13页 245K
描述
IC SERIAL INPUT LOADING, 4 us SETTLING TIME, 8-BIT DAC, UUC, Digital to Analog Converter

AD5300BCHIPS 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:DIE,
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.67
最大模拟输出电压:5.5 V最小模拟输出电压:
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:X-XUUC-N
最大线性误差 (EL):0.3906%位数:8
功能数量:1最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:DIE封装形状:UNSPECIFIED
封装形式:UNCASED CHIP峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified标称安定时间 (tstl):4 µs
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:NO LEAD端子位置:UPPER
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

AD5300BCHIPS 数据手册

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AD5300–Typical Performance Characteristics  
0.5  
1.0  
0.5  
0
1.0  
T
= 25؇C  
A
0.4  
0.3  
TUE @ 3V  
T
= 25؇C  
A
INL @ 3V  
0.5  
0
0.2  
DNL @ 5V  
DNL @ 3V  
0.1  
INL @ 5V  
TUE @ 5V  
0
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
–0.5  
–1.0  
–0.5  
–1.0  
T
= 25؇C  
A
0
50  
100  
150  
200  
250  
50  
100  
150  
200  
250  
0
50  
100  
150  
CODE  
200  
250  
0
CODE  
CODE  
Figure 3. Typical DNL Plot  
Figure 4. Typical Total Unadjusted  
Error Plot  
Figure 2. Typical INL Plot  
3
2
1
2500  
1.0  
0.5  
0
V
= 5V  
DD  
V
= 5V  
DD  
V
= 5V  
DD  
2000  
1500  
V
= 3V  
DD  
MAX INL  
ZS ERROR  
FS ERROR  
MAX DNL  
0
MIN DNL  
MIN INL  
1000  
500  
0
–1  
–0.5  
–2  
–3  
–1.0  
–40  
100 110 120 130 140 150 160 170 180190  
50 60 70 80 90  
–40  
0
40  
80  
120  
0
40  
80  
120  
I
A  
DD  
TEMPERATURE – ؇C  
TEMPERATURE – ؇C  
Figure 7. IDD Histogram with  
VDD = 3 V and VDD = 5 V  
Figure 6. Zero-Scale Error and  
Full-Scale Error vs. Temperature  
Figure 5. INL Error and DNL Error  
vs. Temperature  
5
500  
3
T
= 25؇C  
A
DAC LOADED WITH FF HEX  
4
400  
300  
200  
100  
0
DAC LOADED WITH FF HEX  
2
3
T
= 25؇C  
A
2
1
0
V
V
= 5V  
= 3V  
DD  
1
0
DAC LOADED WITH 00 HEX  
DD  
DAC LOADED WITH 00 HEX  
0
5
10  
– mA  
15  
0
50  
100  
150  
200  
250  
0
5
10  
15  
I
CODE  
SOURCE/SINK  
I
– mA  
SOURCE/SINK  
Figure 9. Source and Sink Current  
Capability with VDD = 5 V  
Figure 10. Supply Current vs. Code  
Figure 8. Source and Sink Current  
Capability with VDD = 3 V  
D
REV.  
–6–  
 
 
 
 
 
 

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