Datasheet > 转换器 > 数字电位计> AD5293BRUZ-50-RL7

AD5293BRUZ-50-RL7

更新时间： 2024-01-06 18:46:10

品牌	Logo	应用领域
亚德诺 - ADI		转换器数字电位计电阻器光电二极管 PC
页数	文件大小	规格书
24页	938K
描述
Single-Channel, 1024-Position, 1percent R-Tolerance Digital Potentiometer

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技术参数
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AD5293BRUZ-50-RL7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP14,.25	针数：	14
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.38
Samacsys Confidence：	3	Samacsys Status：	Released
Samacsys PartID：	342632	Samacsys Pin Count：	14
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Small Outline Packages
Samacsys Footprint Name：	14-Lead TSSOP	Samacsys Released Date：	2017-01-11 11:21:59
Is Samacsys：	N	其他特性：	DEVICE SUPPORTS DUAL SUPPLY OPERATION
标称带宽：	0.21 kHz	控制接口：	3-WIRE SERIAL
转换器类型：	DIGITAL POTENTIOMETER	JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e3	长度：	5 mm
湿度敏感等级：	1	标称负供电电压：	-15 V
功能数量：	1	位置数：	1024
端子数量：	14	最高工作温度：	105 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP14,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	+-10.5/+-16.5/21/33 V
认证状态：	Not Qualified	电阻定律：	LINEAR
最大电阻容差：	1%	最大电阻器端电压：	16.5 V
最小电阻器端电压：	-9 V	座面最大高度：	1.2 mm
子类别：	Digital Potentiometers	标称供电电压：	15 V
表面贴装：	YES	技术：	CMOS
标称温度系数：	35 ppm/ °C	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	标称总电阻：	50000 Ω
宽度：	4.4 mm	Base Number Matches：	1

AD5293BRUZ-50-RL7 数据手册

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AD5293

PROGRAMMING THE POTENTIOMETER DIVIDER

TERMINAL VOLTAGE OPERATING RANGE

Voltage Output Operation

The positive V_DDand negative V_SSpower supplies of the AD5293

define the boundary conditions for proper 3-terminal, digital

potentiometer operation. Supply signals present on the A, B,

and W terminals that exceed V_DDor V_SSare clamped by the

internal forward-biased diodes (see Figure 50).

The digital potentiometer easily generates a voltage divider at

wiper-to-B terminal and wiper-to-A terminal that is proportional

to the input voltage at A to B, as shown in Figure 48. Unlike the

polarity of V_DDto GND, which must be positive, voltage across

A to B, W to A, and W to B can be at either polarity.

OUT

Figure 48. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for simplicity,

connecting the A terminal to 30 V and the B terminal to ground

produces an output voltage at the Wiper W to Terminal B that

ranges from 0 V to 30 V − 1 LSB. Each LSB of voltage is equal to

the voltage applied across the A terminal and B terminal, divided

by the 1024 positions of the potentiometer divider. The general

equation defining the output voltage at V_W, with respect to

ground for any valid input voltage applied to Terminal A and

Terminal B, is

Figure 50. Maximum Terminal Voltages Set by V_DDand V_SS

The ground pin of the AD5293 is primarily used as a digital

ground reference. To minimize the digital ground bounce, the

AD5293 ground pin should be joined remotely to common ground.

The digital input control signals to the AD5293 must be referenced

to the device ground pin (GND) to satisfy the logic level defined

in the Specifications section.

1024 − D

V_W(D) =

×V_A+

×V_B

(3)

Power-Up Sequence

1024

Because there are diodes to limit the voltage compliance at the

A, B, and W terminals (see Figure 50), it is important to power

To optimize the wiper position update rate when in voltage

divider mode, it is recommended that the internal 1% resistor

tolerance calibration feature be disabled by programming Bit C2

of the control register (see Table 11).

V_DDand V_SSfirst, before applying any voltage to the A, B, and W

terminals. Otherwise, the diode is forward-biased such that V_DD

and V_SSare powered up unintentionally. The ideal power-up

sequence is GND, V_SS, V_LOGIC, V_DD, the digital inputs, and then

V_A, V_B, and V_W. The order of powering up V_A, V_B, V_W, and the

digital inputs is not important, as long as they are powered after

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

rheostat mode, the output voltage is dependent mainly on the ratio

of the internal resistors, R_WAand R_WB, and not on the absolute

values. Therefore, the temperature drift reduces to 5 ppm/°C.

V_DD, V_SS, and V_LOGIC

Regardless of the power-up sequence and the ramp rates of the

power supplies, the power-on preset activates after V_LOGICis

powered, restoring midscale to the RDAC register.

EXT_CAP CAPACITOR

A 1 μF capacitor to GND must be connected to the EXT_CAP

pin (see Figure 49) on power-up and throughout the operation

of the AD5293. This capacitor must have a voltage rating of ≥7 V.

AD5293

EXT_CAP

1µF

GND

Figure 49. Hardware Setup for the EXT_CAP Pin

Rev. D | Page 21 of 24

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