Preliminary Technical Data
THEORY OF OPERATION
AD5270/AD5271
RDAC REGISTER
The RDAC register directly controls the position of the digital
rheostat wiper. For example, when the RDAC register is loaded
with all zeros, the wiper is connected to Terminal A of the
variable resistor. The RDAC register is a standard logic register;
there is no restriction on the number of changes allowed.
The AD5270 and AD5271 programmable resistors are designed
to operate as true variable resistors for analog signals within the
terminal voltage range of VSS < VTERM < VDD. The resistor wiper
position is determined by the RDAC register contents. The
RDAC register acts as a scratchpad register which allows
unlimited changes of resistance settings. The RDAC register can
be programmed with any position setting using the SPI
interface. Once a desirable wiper position is found, this value
can be stored in a 50-TP memory register. Thereafter, the wiper
position is always restored to that position for subsequent
power-up. The storing of 50-TP data takes approximately TBD;
during this time, the AD5270/1 will be locked preventing any
changes from taking place.
50-TP MEMORY BLOCK
The AD5270/71 contain an array of 50 OTP (One-Time
Programmable) memory words which allow the wiper position
to be programmed up to 50 times. Table 9 shows the memory
map. Once a desirable wiper position is found, this value can be
saved into a 50-TP memory register. Thereafter the wiper
position will always be set at that position for any future ON-
OFF-ON power supply sequence. Command 3, Table 7, is used
to program the contents of the RDAC register to memory. The
first address to be programmed is location 0x01(see Table 9)
and the AD5272/4 increments the 50-TP memory address for
each subsequent program until the memory is full.
The AD5270/1 also feature a patented (filed not yet issued) 1%
end-to-end resistor tolerance. This simplifies precision, rheostat
mode, and open-loop applications where knowledge of absolute
resistance is critical.
WRITE PROTECTION
SERIAL DATA INTERFACE
On power-up, serial data input register write commands for
both the RDAC register and the 50-TP memory registers are
disabled. The RDAC write protect bit, C1 of the control register
(Table 8), is set to 0 by default. This disables any change of the
RDAC register content regardless of the software commands,
except that the RDAC register can be refreshed from the 50-TP
memory using the software reset command (command #4). To
enable programming of the variable resistor wiper position
(programming the RDAC register) the write protect bit C1 of
the control register must first be programmed. This is
accomplished by loading the serial data input register with
Command #7 (Table 7). To enable programming of the 50-TP
memory block bit C0 of the control register, set to 0 by default,
must first be set to ‘1’.
The AD5270/1contain a serial interface (
, SCLK, DIN and
SYNC
SDO), which is compatible with SPI interface standards, as well
as most DSPs. This device allows writing of data via the serial
interface to every register.
INPUT SHIFT REGISTER
For the AD5270/1 the input shift register is 16 bits wide
(Figures 2 and 3). The 16-bit word consists of two unused bits
(should be set to zero), followed by four control bits, and ten
RDAC data bits, for the AD5272 the lower 2 DAC data bits are
don’t cares if the RDAC register is read from or wrote to. Data is
loaded MSB first (Bit 15). The four control bits determine the
function of the software command (Table 7). Figure 4 shows a
timing diagram of a typical AD5270/1 write sequence.
RDAC AND 50-TP WRITE OPERATION
The write sequence begins by bringing the
line low. The
SYNC
The basic mode of setting the variable resistor wiper position
(programming the RDAC register) is accomplished by loading
the serial data input register with Command #1 (Table 7) and
the desired wiper position data. When the desired wiper
position is determined, the user can load the serial data input
register with Command #3 (Table 7) which stores the wiper
position data in a 50-TP memory register. After TBD (μs), the
wiper position is permanently stored in the 50-TP memory.
Programming data to 50-TP consumes approximately 4mA and
takes approximately TBDms, during this time the shift register
is locked preventing any changes from taking place. Bit C3 of
the Control register can be polled to verify that the fuse
program command was successful. No change in supply voltage
is required to program the 50-TP memory however a 1μF
capacitor on the MEM_CAP pin is required (Figure 9). Prior to
50-TP activation, the AD5270 and the AD5271 preset to mid-
scale on power-up.
pin must be held low until the complete data-word is
SYNC
loaded from the DIN pin. When
returns high, the serial
SYNC
data-word is decoded according to the instructions in Table 7.
The command bits (Cx) control the operation of the digital
potentiometer. The data bits (Dx) are the values that are loaded
into the decoded register. The AD5270/1 have an internal
counter that counts a multiple of 16 bits (a frame) for proper
operation. For example, AD5270/1 work with a 32-bit word, but
cannot work properly with a 31-bit or 33-bit word. The
AD5270/1 do not require a continuous SCLK and dynamic
power can be saved by only transmitting clock pulses during a
serial write. All interface pins should be operated at close to the
supply rails to minimize power consumption in the digital input
buffers.
Rev. PrA | Page 11 of 17
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