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AD526BDZ

更新时间： 2022-12-01 19:31:02
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 放大器
页数 文件大小 规格书
15页 1147K
描述
INSTRUMENTATION AMPLIFIER, 500 uV OFFSET-MAX, 4 MHz BAND WIDTH, CDIP16, HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-16

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AD526BDZ 数据手册

 浏览型号AD526BDZ的Datasheet PDF文件第6页浏览型号AD526BDZ的Datasheet PDF文件第7页浏览型号AD526BDZ的Datasheet PDF文件第8页浏览型号AD526BDZ的Datasheet PDF文件第10页浏览型号AD526BDZ的Datasheet PDF文件第11页浏览型号AD526BDZ的Datasheet PDF文件第12页 
AD526  
THEORY OF OPERATION  
TRANSPARENT MODE OF OPERATION  
The AD526 is a complete software programmable gain amplifier  
(SPGA) implemented monolithically with a drift-trimmed  
BiFET amplifier, a laser wafer trimmed resistor network, JFET  
analog switches and TTL compatible gain code latches.  
In the transparent mode of operation, the AD526 will respond  
directly to level changes at the gain code inputs (A0, A1, A2) if  
B is tied high and both CS and CLK are allowed to float low.  
After the gain codes are changed, the AD526’s output voltage  
typically requires 5.5 µs to settle to within 0.01% of the final  
value. Figures 26 to 29 show the performance of the AD526 for  
positive gain code changes.  
A particular gain is selected by applying the appropriate gain  
code (see Table I) to the control logic. The control logic turns  
on the JFET switch that connects the correct tap on the gain  
network to the inverting input of the amplifier; all unselected  
JFET gain switches are off (open). The “on” resistance of the  
gain switches causes negligible gain error since only the  
amplifier’s input bias current, which is less than 150 pA, actu-  
ally flows through these switches.  
A2  
A1  
A0  
+V  
S
0.1␮F  
+5V  
The AD526 is capable of storing the gain code, (latched mode),  
B, A0, A1, A2, under the direction of control inputs CLK and  
CS. Alternatively, the AD526 can respond directly to gain code  
changes if the control inputs are tied low (transparent mode).  
OUT  
FORCE  
9
16  
15  
14  
13  
12  
11  
B
10  
A1 A0  
CS CLK A2  
LOGIC AND LATCHES  
For gains of 8 and 16, a fraction of the frequency compensation  
capacitance (C1 in Figure 32) is automatically switched out of  
the circuit. This increases the amplifier’s bandwidth and im-  
proves its signal settling time and slew rate.  
16  
8
4
2
1
V
OUT  
GAIN NETWORK  
–
+
AD526  
1
2
3
4
5
6
7
8
OUT  
SENSE  
AMPLIFIER  
+V  
S
0.1␮F  
V
C1  
C2  
IN  
–V  
S
V
IN  
OUT  
FORCE  
Figure 33. Transparent Mode  
LATCHED MODE OF OPERATION  
N1  
N2  
The latched mode of operation is shown in Figure 34. When  
either CS or CLK go to a Logic “1,” the gain code (A0, A1, A2,  
B) signals are latched into the registers and held until both CS  
and CLK return to “0.” Unused CS or CLK inputs should be tied  
to ground . The CS and CLK inputs are functionally and electri-  
cally equivalent.  
–V  
OUT  
S
SENSE  
A0  
A1  
A2  
B
C
O
N
T
R
O
L
14k⍀  
L
G = 8  
A
T
3.4k⍀  
RESISTOR  
NETWORK  
C
H
E
S
TIMING SIGNAL  
G = 2  
A2  
A1  
L
O
G
I
1k⍀  
CLK  
CS  
A0  
G = 16  
+V  
S
C
1.7k⍀  
0.1␮F  
+5V  
G = 4  
DIGITAL  
GND  
OUT  
FORCE  
9
1k⍀  
1.7k⍀  
16  
15  
14  
13  
12  
11  
B
10  
ANALOG  
GND2  
ANALOG  
GND1  
A1 A0  
CS CLK A2  
LOGIC AND LATCHES  
Figure 32. Simplified Schematic of the AD526  
16  
8
4
2
1
V
OUT  
GAIN NETWORK  
–
+
AD526  
1
2
3
4
5
6
7
8
OUT  
SENSE  
0.1␮F  
V
IN  
–V  
S
Figure 34. Latched Mode  
REV. D  
–8–  
1...6789101112...15

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