AD526
GROUNDING AND BYPASSING
Utilizing the force and sense outputs of the AD526, as shown in
Figure 38, avoids signal drops along etch runs to low impedance
loads.
Proper signal and grounding techniques must be applied in
board layout so that specified performance levels of precision
data acquisition components, such as the AD526, are not
degraded.
Table II. Logic Table for Figure 38
VOUT/VIN
A2
A1
A0
As is shown in Figure 37, logic and signal grounds should be
separate. By connecting the signal source ground locally to the
AD526 analog ground Pins 5 and 6, gain accuracy of the
AD526 is maintained. This ground connection should not be
corrupted by currents associated with other elements within the
system.
1
2
4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
16
32
64
128
+15V
–15V
0.1F
0.1F
AD574
12-BIT
V
IN
A/D
0.1F 0.1F
–V
CONVERTER
ANALOG ANALOG +V
GROUND 1 GROUND 2
S
S
V
OUT
FORCE
AMP
AD526
V
OUT
SENSE
GAIN
NETWORK
DIGITAL
GROUND
1F
LATCHES AND LOGIC
+5V
Figure 37. Grounding and Bypassing
CLK
A2
A1
A0
+V
+V
S
S
0.1F
0.1F
+5V
+5V
OUT
FORCE
OUT
FORCE
9
16
15
14
13
12
11
B
10
9
16
15
14
13
12
11
B
10
A1 A0
CS CLK A2
A1 A0
CS CLK A2
LOGIC AND LATCHES
LOGIC AND LATCHES
16
8
4
2
1
16
8
4
2
1
V
OUT
GAIN NETWORK
GAIN NETWORK
–
+
–
+
AD526
AD526
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
OUT
SENSE
OUT
SENSE
0.1F
V
IN
0.1F
–V
S
–V
S
Figure 38. Cascaded Operation
REV. D
–10–