AD5260/AD5262
A
B
VO, ID, and VD are interdependent variables. With proper selection
of R2B, an equilibrium will be reached such that VO converges. R2B
can be in series with a discrete resistor to increase the amplitude,
but the total resistance cannot be too large to saturate the output.
W
R2
R1
In both circuits in Figures 21 and 22, the frequency tuning requires
that both RDACs be adjusted to the same settings. Since the two
channels will be adjusted one at a time, an intermediate state will
occur that may not be acceptable for certain applications. As a
result, different devices can also be used in daisy-chained mode so
that parts can be programmed to the same setting simultaneously.
R2 << R1
Figure 24. Lowering the Nominal Resistance
Figures 23 and 24 show that the digital potentiometers change steps
linearly. On the other hand, log taper adjustment is usually pre-
ferred in applications like audio control. Figure 25 shows another
way of resistance scaling. In this circuit, the smaller the R2 with
respect to RAB, the more the pseudo-log taper characteristic behaves.
FREQUENCY
ADJUSTMENT
C
R
2.2nF
10k⍀
VP
A
B
B
C
2.2nF
R
10k⍀
+5V
W
W
A
V
i
U1
OP1177
–5V
V
O
A
AD5262
W
V
R1
O
R1 = R1 = R2B = AD5262
D1 = D2 = 1N4148
VN
B
R2
R2A
2.1k⍀
D1
D2
R2B
10k⍀
B
W
A
R1
Figure 25. Resistor Scaling with Log Adjustment
Characteristics
1k⍀
AMPLITUDE
ADJUSTMENT
RDAC CIRCUIT SIMULATION MODEL
Figure 22. Programmable Oscillator with
Amplitude Control
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the –3 dB bandwidth of the AD5260
(20 kW resistor) measures 310 kHz at half scale. TPC 20 provides
the large signal BODE plot characteristics of the three available
resistor versions 20 kW, 50 kW, and 200 kW. A parasitic simulation
model is shown in Figure 26. Listing I provides a macro model
net list for the 20 kW RDAC.
Resistance Scaling
The AD5260/AD5262 offer 20 kW, 50 kW, and 200 kW nominal
resistance. For users who need lower resistance and still maintain the
numbers of step adjustment, they can parallel multiple devices. For
example, Figure 23 shows a simple scheme of paralleling both
channels of the AD5262. To adjust half of the resistance linearly
per step, users need to program both channels coherently with
the same settings.
RDAC
20k⍀
A
B
V
C
W
DD
C
C
A
B
25pF
25pF
55pF
A2
B2
A1
B1
W
W1
W2
Figure 26. RDAC Circuit Simulation Model for RDAC = 20 kW
LD
Listing I. Macro Model Net List for RDAC
PARAM D=256, RDAC=20E3
Figure 23. Reduce Resistance by Half with Linear
Adjustment Characteristics
*
SUBCKT DPOT (A,W,B)
*
In voltage divider mode, a much lower resistance can be achieved
by paralleling a discrete resistor as shown in Figure 24. The equiva-
lent resistance becomes:
CA
RWA
CW
RWB
CB
*
A
A
W
W
B
0
W
0
B
0
25E-12
{(1-D/256)*RDAC+60}
55E-12
{D/256*RDAC+60}
25E-12
D
256
RWB _eq
=
R1§§ R2 + R
(16)
(17)
(
)
W
Ê
Ë
D ˆ
RWA_eq = 1-
R1§§ R2 + R
(
)
.ENDS DPOT
W
Á
˜
256
¯
REV. 0
–17–
5秒后页面跳转
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