AD5260/AD5262
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure as shown in Figure 6. This applies
to digital input pins CS, SDI, SDO, PR, SHDN, and CLK.
of this data sheet. An internal level shift circuit ensures that the
common-mode voltage range of the three terminals extends
from VSS to VDD regardless of the digital input level.
340⍀
POWER-UP SEQUENCE
LOGIC
Since there are diodes to limit the voltage compliance at termi-
nals A, B, and W (see Figure 9), it is important to power VDD/VSS
first before applying any voltage to terminals A, B, and W. Other-
wise, the diode will be forward biased such that VDD/VSS will be
powered unintentionally and may affect the rest of the user’s circuit.
The ideal power-up sequence is in the following order: GND,
VDD, VSS, VL, Digital Inputs, and VA/B/W. The order of powering
VA, VB, VW, and Digital Inputs is not important as long as they
are powered after VDD/VSS.
Figure 6. ESD Protection of Digital Pins
A, B, W
V
SS
Daisy-Chain Operation
Figure 7. ESD Protection of Resistor Terminals
The serial-data output (SDO) pin contains an open drain
n-channel FET. This output requires a pull-up resistor to trans-
fer data to the next package’s SDI pin. This allows for daisy
chaining several RDACs from a single processor serial data line.
The pull-up resistor termination voltage can be larger than the VDD
supply voltage. It is recommended to increase the Clock period
when using a pull-up resistor to the SDI pin of the following device
in series because capacitive loading at the daisy-chain node
SDO-SDI between devices may induce time delay to subsequent
devices. Users should be aware of this potential problem to achieve
data transfer successfully (see Figure 10). If two AD5260s are daisy-
chained, this requires a total of 16 bits of data. The first 8 bits,
complying with the format shown in Table I, go to U2, and the
second 8 bits with the same format go to U1. The CS should be
kept low until all 16 bits are clocked into their respective serial
registers, and the CS is then pulled high to complete the operation.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as pos-
sible with a minimum conductor length. Ground paths should
have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 mF–0.1 mF disc or chip ceram-
ics capacitors. Low-ESR 1 mF to 10 mF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize any
transient disturbance (see Figure 8). Notice the digital ground
should also be joined remotely to the analog ground to minimize
the ground bounce.
V
DD
V
DD
؉
V
DD
C1
C3
C4
10F
0.1F
0.1F
؉
C2
AD5260
AD5260
U2
SDI SDO
R
P
10F
V
V
SS
GND
U1
SS
2.2k⍀
C MOSI
SDI SDO
SCLK SS
CLK
CLK
CS
CS
Figure 8. Power Supply Bypassing
TERMINAL VOLTAGE OPERATING RANGE
Figure 10. Daisy-Chain Configuration
RDAC STRUCTURE
The AD5260/AD5262 positive VDD and negative VSS power
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on termi-
nals A, B, and W that exceed VDD or VSS will be clamped by the
internal forward biased diodes (see Figure 9).
The RDAC contains a string of equal resistor segments, with an
array of analog switches, that act as the wiper connection. The
number of positions is the resolution of the device. The AD5260/
AD5262 have 256 connection points allowing it to provide better
than 0.4% set-ability resolution. Figure 11 shows an equivalent
structure of the connections between the three terminals that
make up one channel of the RDAC. The SWA and SWB will
always be ON, while one of the switches SW(0) to SW(2N – 1)
will be ON one at a time depending on the resistance position
decoded from the data bits. Since the switch is not ideal, there is
a 60 W wiper resistance, RW. Wiper resistance is a function of
supply voltage and temperature. The lower the supply voltage, the
higher the wiper resistance. Similarly, the higher the temperature,
the higher the wiper resistance. Users should be aware of the
contribution of the wiper resistance when accurate prediction of
the output resistance is needed.
V
DD
A
W
B
V
SS
Figure 9. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the AD5260/AD5262 device is primarily used
as a digital ground reference, which needs to be tied to the PCB’s
common ground. The digital input control signals to the AD5260/
AD5262 must be referenced to the device ground pin (GND),
and must satisfy the logic level defined in the specification table
–8–
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