AD5255
ELECTRICAL CHARACTERISTICS
Single Supply: VDD = 3 V to 5.5 V and −40°C < TA< +85°C, unless otherwise noted.
Dual Supply: VDD = +2.25 V or +2.75 V , VSS = −2.25 V or −2.75 V and −40°C < TA < + 85°C, unless otherwise noted.
Table 2.
Parameter
DYNAMIC CHARACTERISTICS5, 7
Symbol
Conditions
Min Typ1
Max Unit
Bandwidth −3 dB
Total Harmonic Distortion
VW Settling Time
BW
THDW
tS
VDD/VSS = 2.5 V, RAB = 25 kΩ/250 kΩ
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = VDD, VB = 0 V,
125/12
0.05
4/36
kHz
%
µs
VW = 0.50% error band,
code 0x000 to 0x100, RAB = 25 kΩ/250 kΩ
Resistor Noise Spectral Density
Digital Crosstalk
eN_WB
CT
RAB = 25 kΩ/250 kΩ, TA = 25°C
14/45
−80
nV√Hz
dB
VA = VDD, VB = 0 V, measure VW with
adjacent RDAC making full-scale
change
Analog Crosstalk
CAT
Signal input at A0 and measure output
at W1, f = 1 kHz
−72
dB
INTERFACE TIMING CHARACTERISTICS
(apply to all parts) (Notes8, 9
SCL Clock Frequency
tBUF Bus Free Time between Stop and
Start
)
fSCL
t1
400
kHz
µs
1.3
tHD;STA Hold Time (Repeated Start)
t2
After this period the first clock pulse is
generated
600
ns
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Start Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tR Rise Time of Both SDA and SCL
Signals
t3
t4
t5
t6
t7
t8
1.3
0.6
600
µs
µs
ns
ns
ns
ns
50
900
100
300
300
tF Fall Time of Both SDA and SCL
Signals
t9
ns
tSU;STO Setup Time for Stop Condition
EEMEM Data Storing Time
EEMEM Data Restoring Time at
Power-On
t10
600
ns
ms
µs
tEEMEM_STORE
tEEMEM_RESTORE1
26
360
EEMEM Data Restoring Time on
Restore
tEEMEM_RESTORE2
360
µs
Command or Reset Operation
EEMEM Data Rewritable Time
FLASH/EE MEMORY RELIABILITY
Endurance10
tEEMEM_REWRITE
540
100
µs
kcycles
years
Data Retention11
55°C
100
1 Typical represent average readings at 25°C, VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
4 Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
7 All dynamic characteristics use VDD = 5 V.
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 See the timing diagram for location of measured values.
10 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at −40°C, +25°C, and +85°C, typical endurance at 25°C is 700,000 cycles.
11 Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV
derates with junction temperature.
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