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AD5254BRU50-RL7

更新时间： 2024-01-16 09:51:09
品牌 Logo 应用领域
亚德诺 - ADI 转换器电位器数字电位计存储电阻器光电二极管
页数 文件大小 规格书
28页 1160K
描述
Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers

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AD5254BRU50-RL7 技术参数

Source Url Status Check Date：2013-05-01 14:56:11.245是否无铅： 含铅
是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：MO-153AC, TSSOP-20
针数：20Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.35Is Samacsys：N
其他特性：NONVOLATILE MEMORY; DEVICE SUPPORTS DUAL SUPPLY OPERATION标称带宽：0.08 kHz
控制接口：2-WIRE SERIAL转换器类型：DIGITAL POTENTIOMETER
JESD-30 代码：R-PDSO-G20JESD-609代码：e0
长度：6.5 mm湿度敏感等级：1
标称负供电电压：-2.5 V功能数量：4
位置数：256端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：240
电源：3/5 V认证状态：Not Qualified
电阻定律：LINEAR最大电阻容差：20%
最大电阻器端电压：2.75 V最小电阻器端电压：-2.25 V
座面最大高度：1.2 mm子类别：Digital Potentiometers
标称供电电压：2.5 V表面贴装：YES
技术：CMOS标称温度系数：650 ppm/ °C
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
标称总电阻：50000 Ω宽度：4.4 mm
Base Number Matches：1

AD5254BRU50-RL7 数据手册

 浏览型号AD5254BRU50-RL7的Datasheet PDF文件第4页浏览型号AD5254BRU50-RL7的Datasheet PDF文件第5页浏览型号AD5254BRU50-RL7的Datasheet PDF文件第6页浏览型号AD5254BRU50-RL7的Datasheet PDF文件第8页浏览型号AD5254BRU50-RL7的Datasheet PDF文件第9页浏览型号AD5254BRU50-RL7的Datasheet PDF文件第10页 
AD5253/AD5254  
INTERFACE TIMING CHARACTERISTICS (ALL PARTS)  
Guaranteed by design, not subject to production test. See Figure 23 for location of measured values. All input control voltages are specified  
with tR = tF = 2.5 ns (10ꢀ to 90ꢀ of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both  
VDD = 3 V and 5 V. When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the  
I2C interface at these pins conducts current of about 0.8 mA at VDD = 5.5 V and 0.2 mA at VDD = 2.7 V.  
Table 3.  
Parameter  
Symbol  
Conditions  
Min Typ1 Max Unit  
SCL Clock Frequency  
tBUF Bus Free Time between STOP and START  
tHD;STA Hold Time (Repeated START)  
fSCL  
t1  
t2  
400  
kHz  
µs  
µs  
1.3  
0.6  
After this period, the first clock pulse is  
generated  
tLOW Low Period of SCL Clock  
tHIGH High Period of SCL Clock  
tSU;STA Setup Time for START Condition  
tHD;DAT Data Hold Time  
tSU;DAT Data Setup Time  
t3  
t4  
t5  
t6  
t7  
t8  
t9  
t10  
1.3  
0.6  
0.6  
0
µs  
µs  
µs  
µs  
ns  
ns  
ns  
µs  
ms  
µs  
0.9  
100  
tF Fall Time of Both SDA and SCL Signals  
tR Rise Time of Both SDA and SCL Signals  
tSU;STO Setup Time for STOP Condition  
EEMEM Data Storing Time  
300  
300  
0.6  
tEEMEM_STORE  
26  
300  
EEMEM Data Restoring Time at Power On9  
tEEMEM_RESTORE1 VDD rise time dependent. Measure without  
decoupling capacitors at VDD and VSS.  
EEMEM Data Restoring Time upon Restore  
Command or RESET Operation9  
tEEMEM_RESTORE2 VDD = 5 V  
300  
540  
µs  
µs  
EEMEM Data Rewritable Time10  
FLASH/EE MEMORY RELIABILITY  
Endurance11  
tEEMEM_REWRITE  
100  
kCycles  
Years  
Data Retention12  
100  
1 Typical values represent average readings at 25°C and VDD = 5 V.  
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 kΩ  
version at VDD = 2.7V, IW = VDD/R for both VDD = 3 V or VDD = 5 V.  
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL  
specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.  
4 Resistor terminals A, B, and W have no limitations on polarity with respect to each other.  
5 Guaranteed by design and not subject to production test.  
6 cmd 0 NOP should be activated after cmd 1 in order to minimize IDD_RESTORE current consumption.  
7 PDISS is calculated from (IDD × VDD = 5 V).  
8 All dynamic characteristics use VDD = 5 V.  
9 During power-up, all outputs preset to midscale before restoring EEMEM contents. RDAC0 has the shortest whereas RDAC3 has the longest EEMEM restore time.  
10 Delay time after power-on or RESET before new EEMEM data to be written.  
11 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.  
12 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates  
with junction temperature.  
Rev. 0 | Page 7 of 28  
 
 
 
 
 
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