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AD524SD/883B PDF预览

AD524SD/883B

更新时间： 2024-01-15 18:03:17
品牌 Logo 应用领域
亚德诺 - ADI 仪表放大器放大器电路
页数 文件大小 规格书
16页 395K
描述
Precision Instrumentation Amplifier

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AD524SD/883B 技术参数

Source Url Status Check Date：2013-05-01 14:56:11.133是否无铅： 含铅
是否Rohs认证： 不符合生命周期：Not Recommended
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.31.00.01
风险等级：5.04放大器类型：INSTRUMENTATION AMPLIFIER
最大平均偏置电流 (IIB)：0.05 µA标称带宽 (3dB)：1 MHz
最小共模抑制比：70 dB最大输入失调电流 (IIO)：0.035 µA
最大输入失调电压：100 µVJESD-30 代码：R-CDIP-T16
JESD-609代码：e0长度：19.05 mm
负供电电压上限：-18 V标称负供电电压 (Vsup)：-15 V
最大非线性：0.01%功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：+-15 V
认证状态：Not Qualified筛选级别：MIL-STD-883 Class B
座面最大高度：5.08 mm标称压摆率：5 V/us
子类别：Instrumentation Amplifier最大压摆率：5 mA
供电电压上限：18 V标称供电电压 (Vsup)：15 V
表面贴装：NO温度等级：MILITARY
端子面层：Tin/Lead (Sn63Pb37)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED最大电压增益：1000
最小电压增益：1标称电压增益：10
宽度：7.62 mmBase Number Matches：1

AD524SD/883B 数据手册

 浏览型号AD524SD/883B的Datasheet PDF文件第5页浏览型号AD524SD/883B的Datasheet PDF文件第6页浏览型号AD524SD/883B的Datasheet PDF文件第7页浏览型号AD524SD/883B的Datasheet PDF文件第9页浏览型号AD524SD/883B的Datasheet PDF文件第10页浏览型号AD524SD/883B的Datasheet PDF文件第11页 
AD524  
As RG is reduced to increase the programmed gain, the trans-  
conductance of the input preamp increases to the transconduct-  
ance of the input transistors. This has three important advantages.  
First, this approach allows the circuit to achieve a very high  
open loop gain of 3 × 108 at a programmed gain of 1000, thus  
reducing gain-related errors to a negligible 30 ppm. Second, the  
gain bandwidth product, which is determined by C3 or C4 and  
the input transconductance, reaches 25 MHz. Third, the input  
voltage noise reduces to a value determined by the collector  
current of the input transistors for an RTI noise of 7 nV/√Hz at  
G = 1000.  
10k⍀  
0.01%  
10k⍀  
0.1%  
1k⍀  
10T  
INPUT  
20V p-p  
V
OUT  
100k⍀  
0.1%  
+V  
S
RG  
1
G = 10  
G = 100  
AD524  
11k⍀  
0.1%  
100⍀  
0.1%  
1k⍀  
0.1%  
G = 1000  
RG  
2
–V  
S
Figure 27. Settling Time Test Circuit  
INPUT PROTECTION  
As interface amplifiers for data acquisition systems, instrumen-  
tation amplifiers are often subjected to input overloads, i.e.,  
voltage levels in excess of the full scale for the selected gain  
range. At low gains, 10 or less, the gain resistor acts as a current  
limiting element in series with the inputs. At high gains the  
lower value of RG will not adequately protect the inputs from  
excessive currents. Standard practice would be to place series  
limiting resistors in each input, but to limit input current to  
below 5 mA with a full differential overload (36 V) would re-  
quire over 7k of resistance which would add 10 nV√Hz of noise.  
To provide both input protection and low noise a special series  
protect FET was used.  
+V  
S
I
I
2
1
V
B
50␮A  
50␮A  
R52  
A1  
A2  
C4  
20k⍀  
SENSE  
R53  
C3  
20k⍀  
A3  
V
R57  
20k⍀  
O
CH ,  
2
R56  
20k⍀  
R54  
20k⍀  
CH , CH  
3
4
R55  
20k⍀  
Q1, Q3  
Q2, Q4  
–IN  
4.44k⍀  
REFERENCE  
+IN  
CH  
1
CH , CH ,  
2
CH  
3
RG  
RG  
2
1
404⍀  
40⍀  
4
A unique FET design was used to provide a bidirectional cur-  
rent limit, thereby, protecting against both positive and negative  
overloads. Under nonoverload conditions, three channels CH2,  
CH3, CH4, act as a resistance (≈1 kΩ) in series with the input as  
before. During an overload in the positive direction, a fourth  
channel, CH1, acts as a small resistance (≈3 kΩ) in series with  
the gate, which draws only the leakage current, and the FET  
limits IDSS. When the FET enhances under a negative overload,  
the gate current must go through the small FET formed by CH1  
and when this FET goes into saturation, the gate current is  
limited and the main FET will go into controlled enhancement.  
The bidirectional limiting holds the maximum input current to  
3 mA over the 36 V range.  
G100  
G1000  
I
3
I
4
50␮A  
CH  
50␮A  
1
–V  
S
Figure 28 Simplified Circuit of Amplifier; Gain Is Defined as  
((R56 + R57)/(RG)) + 1. For a Gain of 1, RG Is an Open Circuit  
Theory of Operation  
The AD524 is a monolithic instrumentation amplifier based on  
the classic 3 op amp circuit. The advantage of monolithic con-  
struction is the closely matched components that enhance the  
performance of the input preamp. The preamp section develops  
the programmed gain by the use of feedback concepts. The  
programmed gain is developed by varying the value of RG (smaller  
values increase the gain) while the feedback forces the collector  
currents Q1, Q2, Q3 and Q4 to be constant, which impresses  
the input voltage across RG.  
INPUT OFFSET AND OUTPUT OFFSET  
Voltage offset specifications are often considered a figure of  
merit for instrumentation amplifiers. While initial offset may be  
adjusted to zero, shifts in offset voltage due to temperature  
variations will cause errors. Intelligent systems can often correct  
for this factor with an autozero cycle, but there are many small-  
signal high-gain applications that don’t have this capability.  
+V  
S
AD712  
+V  
s
10  
16.2k⍀  
100  
AD524  
1␮F  
DUT  
1000  
1/2  
RG  
2
1/2  
1␮F  
9.09k⍀  
1k⍀  
1␮F  
16.2k⍀  
1.82k⍀  
G1, 10, 100  
G1000  
–V  
–V  
S
S
100⍀  
1.62M⍀  
Figure 29. Noise Test Circuit  
–8–  
REV. E  
1...567891011...16

中文翻译

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AD524SD/883B 替代型号

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AD524SD/883B ADI

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