Datasheet > AD5246

AD5246

更新时间： 2022-12-11 21:11:36

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	913K
描述
128-Position I2C Compatible Digital Resistor

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AD5246 数据手册

AD5246

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

Table 2. V_DD= 5 V 1ꢀ0 or 3 V 1ꢀ0; V_A= V_DD; –4ꢀ°C < T_A< +125°C; unless otherwise noted

Parameter

Symbol Conditions

Min Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

R_WB

R-DNL

R-INL

∆R_AB

R_WB, V_A= No Connect

T_A= 25°C

–1

–2

–20

0.1

0.25

+20

LSB

ppm/°C

Ω

∆R_AB/∆T Wiper = No Connect

R_WB

150

Code=0x00, V_DD= 5 V

Code=0x00, V_DD= 2.7 V

150

400

Ω

RESISTOR TERMINALS

Voltage Range⁴

V_{B, W}

C_B

C_W

I_CM

GND

V_DD

Capacitance⁵B

f = 1 MHz, Measured to GND, Code = 0x40

f = 1 MHz, measured to GND, Code = 0x40

Capacitance⁵W

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

Input Logic Low

Input Logic High

Input Logic Low

Input Current

Input Capacitance⁵

V_IH

V_IL

V_IH

V_IL

I_IL

V_DD= 5 V

V_DD= 3 V

2.4

2.1

µA

0.8

0.6

V_IN= 0 V or 5 V

C_IL

POWER SUPPLIES

Power Supply Range

Supply Current

Power Dissipation⁶

Power Supply Sensitivity

DYNAMIC CHARACTERISTICS^{5, 7}

Bandwidth –3 dB

Total Harmonic Distortion

V_WSettling Time (10 kΩ/50 kΩ/100 kΩ)

Resistor Noise Voltage Density

V_{DD RANGE}

I_DD

P_DISS

2.7

5.5

µA

µW

V_IH= 5 V or V_IL= 0 V

V_IH= 5 V or V_IL= 0 V, V_DD= 5 V

V_DD= +5 V 10%, Code = Midscale

PSSR

0.01

0.02 %/%

THD_W

t_S

R_AB= 10 kΩ/50 kΩ/100 kΩ, Code = 0x40

V_A=1 V rms, f = 1 kHz, R_AB= 10 kΩ

V_A= 5 V 1 LSB Error Band

600/100/40

0.05

kHz

µs

e_{N_WB}

R_WB= 5 kΩ, R_S= 0

nV/√Hz

¹Typical specifications represent average readings at +25°C and V_DD= 5 V.

²Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

³Code = 0x7F.

⁴Resistor terminals A and W have no limitations on polarity with respect to each other.

⁵Guaranteed by design and not subject to production test.

⁶P_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

⁷All dynamic characteristics use V_DD= 5 V.

Rev. 0 | Page 4 of 20

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