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AD5246

更新时间： 2022-12-11 21:11:36

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	913K
描述
128-Position I2C Compatible Digital Resistor

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AD5246 数据手册

AD5246

TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

Table 3. V_DD= 5 V 1ꢀ0 or 3 V 1ꢀ0; V_A= V_DD; –4ꢀ°C < T_A< +125°C; unless otherwise noted

Parameter

Symbol

Conditions

Min Typ¹Max Unit

I²C INTERFACE TIMING CHARACTERISTICS^{2, 3}

(Specifications Apply to All Parts)

SCL Clock Frequency

t_BUFBus Free Time between STOP and START

t_HD;STAHold Time (Repeated START)

f_SCL

t₁

t₂

400

kHz

µs

1.3

After this period, the first clock pulse is

generated.

0.6

1.3

0.6

µs

t_LOWLow Period of SCL Clock

t_HIGHHigh Period of SCL Clock

t_SU;STASetup Time for Repeated START Condition

t_HD;DATData Hold Time

t_SU;DATData Setup Time

t_FFall Time of Both SDA and SCL Signals

t_RRise Time of Both SDA and SCL Signals

t_SU;STOSetup Time for STOP Condition

t₃

t₄

t₅

t₆

t₇

t₈

t₉

t₁₀

0.9

100

0.6

300

¹Typical specifications represent average readings at 25°C and V_DD= 5 V.

²Guaranteed by design and not subject to production test.

³See timing diagrams (Figure 25, Figure 26, Figure 27) for locations of measured values.

Rev. 0 | Page 5 of 20

1 2 3 456 7 8...20

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