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AD5245BRJZ10-RL7 PDF预览

AD5245BRJZ10-RL7

更新时间: 2024-01-13 16:14:05
品牌 Logo 应用领域
亚德诺 - ADI 转换器数字电位计电阻器光电二极管
页数 文件大小 规格书
20页 687K
描述
256-Position I2C-Compatible Digital Potentiometer

AD5245BRJZ10-RL7 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:LSSOP, TSSOP8,.1针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.11
其他特性:IT CAN ALSO OPERATE WITH 5V NOMINAL SUPPLY标称带宽:0.6 kHz
控制接口:2-WIRE SERIAL转换器类型:DIGITAL POTENTIOMETER
JESD-30 代码:R-PDSO-G8JESD-609代码:e4
长度:2.9 mm湿度敏感等级:1
功能数量:1位置数:256
端子数量:8最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装等效代码:TSSOP8,.1
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3/5 V
认证状态:Not Qualified电阻定律:LINEAR
最大电阻容差:30%最大电阻器端电压:3 V
最小电阻器端电压:座面最大高度:1.45 mm
子类别:Digital Potentiometers标称供电电压:3 V
表面贴装:YES标称温度系数:45 ppm/ °C
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
标称总电阻:10000 Ω宽度:1.6 mm
Base Number Matches:1

AD5245BRJZ10-RL7 数据手册

 浏览型号AD5245BRJZ10-RL7的Datasheet PDF文件第11页浏览型号AD5245BRJZ10-RL7的Datasheet PDF文件第12页浏览型号AD5245BRJZ10-RL7的Datasheet PDF文件第13页浏览型号AD5245BRJZ10-RL7的Datasheet PDF文件第15页浏览型号AD5245BRJZ10-RL7的Datasheet PDF文件第16页浏览型号AD5245BRJZ10-RL7的Datasheet PDF文件第17页 
AD5245  
PROGRAMMING THE POTENTIOMETER DIVIDER  
TERMINAL VOLTAGE OPERATING RANGE  
Voltage Output Operation  
The AD5245 VDD and GND power supply defines the boundary  
conditions for proper 3-terminal digital potentiometer  
operation. Supply signals present on Terminals A, B, and W that  
exceed VDD or GND are clamped by the internal forward-biased  
diodes (see Figure 40).  
The digital potentiometer easily generates a voltage divider at  
wiper-to-B and wiper-to-A proportional to the input voltage at  
A to B. Unlike the polarity of VDD to GND, which must be  
positive, voltage across A to B, W to A, and W to B can be at  
either polarity.  
V
DD  
A
V
I
W
B
A
B
W
V
O
GND  
Figure 40. Maximum Terminal Voltages Set by VDD and GND  
Figure 37. Potentiometer Mode Configuration  
POWER-UP SEQUENCE  
If ignoring the effect of the wiper resistance for approximation,  
then connecting the A terminal to 5 V and the B terminal to  
ground produces an output voltage at the wiper-to-B starting at  
0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the  
voltage applied across Terminal A and B divided by the 256  
positions of the potentiometer divider. The general equation  
defining the output voltage at VW with respect to ground for any  
valid input voltage applied to Terminals A and B is  
Because the ESD protection diodes limit the voltage compliance  
at Terminals A, B, and W (see Figure 40), it is important to  
power VDD and GND before applying any voltage to Terminals  
A, B, and W; otherwise, the diode is forward biased such that  
VDD is powered unintentionally and can affect the rest of the  
users circuit. The ideal power-up sequence is in the following  
order: GND, VDD, digital inputs, and then VA, VB, and VW. The  
relative order of powering VA, VB, VW, and the digital inputs is  
not important as long as they are powered after VDD and GND.  
D
256  
256 D  
256  
VW (D) =  
VA +  
VB  
(3)  
LAYOUT AND POWER SUPPLY BYPASSING  
A more accurate calculation, which includes the effect of wiper  
resistance, VW, is  
It is good practice to employ compact, minimum lead length  
layout design. The leads to the inputs should be as direct as  
possible with a minimum conductor length. Ground paths  
should have low resistance and low inductance.  
R
WB (D)  
RAB  
R
WA (D)  
RAB  
VW (D) =  
VA +  
VB  
(4)  
Similarly, it is also good practice to bypass the power supplies  
with quality capacitors for optimum stability. Supply leads to  
the device should be bypassed with disk or chip ceramic  
capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum  
or electrolytic capacitors should also be applied at the supplies  
to minimize any transient disturbance and low frequency ripple  
(see Figure 41). Note that the digital ground should also be  
joined remotely to the analog ground at one point to minimize  
the ground bounce.  
Operation of the digital potentiometer in the divider mode  
results in a more accurate operation over temperature. Unlike  
the rheostat mode, the output voltage is dependent mainly on  
the ratio of the internal resistors, RWA and RWB, not the absolute  
values. Therefore, the temperature drift reduces to 15 ppm/°C.  
ESD PROTECTION  
All digital inputs are protected with a series of input resistors and  
parallel Zener ESD structures, shown in Figure 38 and Figure 39.  
This applies to the digital input pins SDA, SCL, and AD0.  
340  
V
V
DD  
DD  
LOGIC  
+
C3  
C1  
10µF  
0.1µF  
AD5245  
GND  
Figure 38. ESD Protection of Digital Pins  
GND  
A, B, W  
GND  
Figure 41. Power Supply Bypassing  
Figure 39. ESD Protection of Resistor Terminals  
Rev. B | Page 14 of 20  
 
 
 
 
 

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