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AD5243BRM2.5

更新时间： 2024-01-23 15:56:13
品牌 Logo 应用领域
亚德诺 - ADI 转换器数字电位计电阻器光电二极管
页数 文件大小 规格书
20页 1067K
描述
Dual 256-Position I2C Compatible Digital Potentiometer

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中文翻译

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AD5243BRM2.5 技术参数

Source Url Status Check Date：2013-05-01 14:56:11.03是否无铅： 含铅
是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：3 X 4.90 MM, MO-187BA, MSOP-10
针数：10Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：8.12其他特性：IT ALSO OPERATES AT 5 V SUPPLY
标称带宽：4.8 kHz控制接口：2-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：S-PDSO-G10
JESD-609代码：e0长度：3 mm
湿度敏感等级：1功能数量：2
位置数：256端子数量：10
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP10,.19,20封装形状：SQUARE
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：240
电源：3/5 V认证状态：Not Qualified
电阻定律：LINEAR最大电阻容差：55%
最大电阻器端电压：5.5 V最小电阻器端电压：
座面最大高度：1.1 mm子类别：Digital Potentiometers
标称供电电压：3 V表面贴装：YES
标称温度系数：35 ppm/ °C温度等级：AUTOMOTIVE
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：20标称总电阻：2500 Ω
宽度：3 mmBase Number Matches：1

AD5243BRM2.5 数据手册

 浏览型号AD5243BRM2.5的Datasheet PDF文件第11页浏览型号AD5243BRM2.5的Datasheet PDF文件第12页浏览型号AD5243BRM2.5的Datasheet PDF文件第13页浏览型号AD5243BRM2.5的Datasheet PDF文件第15页浏览型号AD5243BRM2.5的Datasheet PDF文件第16页浏览型号AD5243BRM2.5的Datasheet PDF文件第17页 
AD5243/AD5248  
340Ω  
Typical device-to-device matching is process lot dependent and  
may vary by up to 30ꢀ. Because the resistance element is  
processed in thin film technology, the change in RAB with  
temperature has a very low 35 ppm/°C temperature coefficient.  
LOGIC  
GND  
Figure 39. ESD Protection of Digital Pins  
PROGRAMMING THE POTENTIOMETER DIVIDER  
Voltage Output Operation  
A, B, W  
The digital potentiometer easily generates a voltage divider at  
wiper-to-B and wiper-to-A proportional to the input voltage at  
A to B. Unlike the polarity of VDD to GND, which must be  
positive, voltage across A to B, W to A, and W to B can be at  
either polarity.  
GND  
Figure 40. ESD Protection of Resistor Terminals  
TERMINAL VOLTAGE OPERATING RANGE  
The AD5243/AD5248 VDD and GND power supply defines the  
boundary conditions for proper 3-terminal digital potentiome-  
ter operation. Supply signals present on Terminals A, B, and W  
that exceed VDD or GND are clamped by the internal forward  
biased diodes (see Figure 41).  
V
I
A
W
V
O
B
V
DD  
Figure 38. Potentiometer Mode Configuration  
A
If ignoring the effect of the wiper resistance for approximation,  
connecting the A terminal to 5 V and the B terminal to ground  
produces an output voltage at the wiper-to-B starting at 0 V up  
to 1 LSB less than 5 V. Each LSB of voltage is equal to the volt-  
age applied across terminal AB divided by the 256 positions of  
the potentiometer divider. The general equation defining the  
output voltage at VW with respect to ground for any valid input  
voltage applied to terminals A and B is  
W
B
GND  
Figure 41. Maximum Terminal Voltages Set by VDD and GND  
POWER-UP SEQUENCE  
Because the ESD protection diodes limit the voltage compliance  
at Terminals A, B, and W (see Figure 41), it is important to  
power VDD/GND before applying any voltage to Terminals A, B,  
and W% otherwise, the diode is forward biased such that VDD is  
powered unintentionally and may affect the rest of the user’s  
circuit. The ideal power-up sequence is in the following order:  
GND, VDD, digital inputs, and then VA, VB, and VW. The relative  
order of powering VA, VB, VW, and the digital inputs is not  
important as long as they are powered after VDD/GND.  
D
256  
256 − D  
256  
VW (D) =  
VA +  
VB  
(3)  
A more accurate calculation, which includes the effect of wiper  
resistance, VW, is  
RWB (D)  
RWA(D)  
RAB  
(4)  
VW (D) =  
VA +  
VB  
RAB  
Operation of the digital potentiometer in the divider mode  
results in a more accurate operation overtemperature. Unlike  
the rheostat mode, the output voltage is dependent mainly on  
the ratio of the internal resistors RWA and RWB and not the  
absolute values. Therefore, the temperature drift reduces to  
15 ppm/°C.  
LAYOUT AND POWER SUPPLY BYPASSING  
It is good practice to employ compact, minimum lead length  
layout design. The leads to the inputs should be as direct as  
possible with a minimum conductor length. Ground paths  
should have low resistance and low inductance.  
ESD PROTECTION  
Similarly, it is also good practice to bypass the power supplies  
with quality capacitors for optimum stability. Supply leads to the  
device should be bypassed with disk or chip ceramic capacitors  
of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electro-  
lytic capacitors should also be applied at the supplies to  
minimize any transient disturbance and low frequency ripple  
(see Figure 42). Note that the digital ground should also be  
joined remotely to the analog ground at one point to minimize  
the ground bounce.  
All digital inputs are protected with a series of input resistors  
and parallel Zener ESD structures, shown in Figure 39 and  
Figure 40. This applies to the digital input pins SDA, SCL, AD0,  
and AD1 (AD5248 only).  
Rev. 0 | Page 14 of 20  
 
 
 
 
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中文翻译

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AD5243BRM2.5 替代型号

型号 品牌 替代类型 描述 数据表
AD5243BRMZ2.5-RL7 ADI

完全替代

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完全替代

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