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AD5242BRZ100-REEL7 PDF预览

AD5242BRZ100-REEL7

更新时间: 2024-02-20 20:49:59
品牌 Logo 应用领域
亚德诺 - ADI 转换器电位器数字电位计电阻器光电二极管
页数 文件大小 规格书
20页 550K
描述
I2C-Compatible, 256-Position Digital Potentiometers

AD5242BRZ100-REEL7 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknown风险等级:5.82
其他特性:IT CAN ALSO OPERATE FROM A 3V NOM SINGLE SUPPLY OR +/-2.3V TO +/-2.7V DUAL SUPPLY标称带宽:0.069 kHz
控制接口:2-WIRE SERIAL转换器类型:DIGITAL POTENTIOMETER
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:9.9 mm湿度敏感等级:1
标称负供电电压:-2.5 V功能数量:2
位置数:256端子数量:16
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:COMMERCIAL
电阻定律:LINEAR最大电阻容差:50%
最大电阻器端电压:5.5 V最小电阻器端电压:-2.3 V
座面最大高度:1.75 mm标称供电电压:2.5 V
表面贴装:YES标称温度系数:30 ppm/ °C
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
标称总电阻:100000 Ω宽度:3.9 mm

AD5242BRZ100-REEL7 数据手册

 浏览型号AD5242BRZ100-REEL7的Datasheet PDF文件第11页浏览型号AD5242BRZ100-REEL7的Datasheet PDF文件第12页浏览型号AD5242BRZ100-REEL7的Datasheet PDF文件第13页浏览型号AD5242BRZ100-REEL7的Datasheet PDF文件第15页浏览型号AD5242BRZ100-REEL7的Datasheet PDF文件第16页浏览型号AD5242BRZ100-REEL7的Datasheet PDF文件第17页 
AD5241/AD5242  
4. Unlike the write mode, the data byte follows immediately  
after the acknowledgment of the slave address byte in  
Frame 2 read mode. Data is transmitted over the serial bus  
in sequences of nine clock pulses (slightly different from  
the write mode, there are eight data bits followed by a no  
acknowledge Logic 1 bit in read mode). Similarly, the  
transitions on the SDA line must occur during the low  
period of SCL and remain stable during the high period of  
SCL (see Figure 5).  
5. When all data bits have been read or written, a stop condition  
is established by the master. A stop condition is defined as  
a low-to-high transition on the SDA line while SCL is high.  
In write mode, the master pulls the SDA line high during  
the tenth clock pulse to establish a stop condition (see  
Figure 4). In read mode, the master issues a no acknowledge  
for the ninth clock pulse (that is, the SDA line remains high).  
The master then brings the SDA line low before the tenth  
clock pulse, which goes high to establish a stop condition  
(see Figure 5).  
MULTIPLE DEVICES ON ONE BUS  
Figure 33 shows four AD5242 devices on the same serial bus.  
Each has a different slave address because the state of their AD0  
and AD1 pins are different. This allows each RDAC within each  
device to be written to or read from independently. The master  
device output bus line drivers are open-drain pull-downs in a  
fully I2C-compatible interface. Note, a device is addressed properly  
only if the bit information of AD0 and AD1 in the slave address  
byte matches with the logic inputs at the AD0 and AD1 pins of  
that particular device.  
LEVEL-SHIFT FOR BIDIRECTIONAL INTERFACE  
While most old systems can operate at one voltage, a new  
component may be optimized at another. When they operate  
the same signal at two different voltages, a proper method of  
level-shifting is needed. For instance, a 3.3 V E2PROM can be  
used to interface with a 5 V digital potentiometer. A level-shift  
scheme is needed to enable a bidirectional communication so that  
the setting of the digital potentiometer can be stored to and  
retrieved from the E2PROM. Figure 32 shows one of the techniques.  
M1 and M2 can be N-channel FETs (2N7002) or low threshold  
FDV301N if VDD falls below 2.5 V.  
A repeated write function gives the user flexibility to update the  
RDAC output a number of times after addressing and instructing  
the part only once. During the write cycle, each data byte updates  
the RDAC output. For example, after the RDAC has acknowledged  
its slave address and instruction bytes, the RDAC output is  
updated. If another byte is written to the RDAC while it is still  
addressed to a specific slave device with the same instruction,  
this byte updates the output of the selected slave device. If  
different instructions are needed, the write mode has to start a  
completely new sequence with a new slave address, instruction,  
and data bytes transferred again. Similarly, a repeated read  
function of the RDAC is also allowed.  
V
= 3.3V  
V
= 5V  
DD  
DD  
RP  
RP  
RP  
RP  
G
S
D
SDA1  
SCL1  
SDA2  
M1  
G
S
D
SCL2  
M2  
3.3V  
5V  
AD5242  
2
E PROM  
Figure 32. Level-Shift for Different Voltage Devices Operation  
READBACK RDAC VALUE  
Specific to the AD5242 dual-channel device, the channel of  
interest is the one that was previously selected in the write mode.  
In addition, to read both RDAC values consecutively, users have to  
perform two write-read cycles. For example, users may first specify  
the RDAC1 subaddress in write mode (it is not necessary to issue  
the data byte and stop condition), and then change to read mode  
to read the RDAC1 value. To continue reading the RDAC2 value,  
users have to switch back to write mode, specify the subaddress,  
and then switch once again to read mode to read the RDAC2  
value. It is not necessary to issue the write mode data byte or  
the first stop condition for this operation. Users should refer to  
Figure 4 and Figure 5 for the programming format.  
5V  
R
R
P
P
SDA  
SCL  
MASTER  
V
V
V
DD  
DD  
DD  
SDA SCL  
SDA SCL  
AD1  
SDA SCL  
AD1  
SDA SCL  
AD1  
AD1  
AD0  
AD0  
AD0  
AD0  
AD5242  
AD5242  
AD5242  
AD5242  
Figure 33. Multiple AD5242 Devices on One Bus  
Rev. C | Page 1ꢀ of 20  
 
 
 

AD5242BRZ100-REEL7 替代型号

型号 品牌 替代类型 描述 数据表
AD5242BRZ100-REEL7 ADI

当前型号

I2C-Compatible, 256-Position Digital Potentiometers
AD5242BRZ1M ADI

类似代替

I2C-Compatible, 256-Position Digital Potentiometers
AD5242BR100-REEL7 ADI

完全替代

I2C Compatible 256-Position Digital Potentiometers

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