Datasheet > AD5241BRU1M

AD5241BRU1M

更新时间： 2024-01-04 17:32:15

品牌	Logo	应用领域
亚德诺 - ADI		电位器
页数	文件大小	规格书
20页	550K
描述
I2C-Compatible, 256-Position Digital Potentiometers

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数据手册

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AD5241BRU1M 数据手册

AD5241/AD5242

TIMING DIAGRAMS

t₈

SDA

SCL

t₁

t₈

t₉

t₂

t₄

t₂

t₇

t₅

t₁₀

t₃

t₆

Figure 3. Detail Timing Diagram

Data of AD5241/AD5242 is accepted from the I²C bus in the following serial format.

Table 2.

AD1 AD0

RS SD O₁O₂

Instruction Byte

D7 D6 D5 D4 D3 D2 D1 D0

Data Byte

Slave Address Byte

where:

S = start condition

P = stop condition

A = acknowledge

X = don’t care

AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at Pins AD1 and AD0.

R/ = Read enable at high and output to SDA. Write enable at low.

/B = RDAC subaddress select; 0 for RDAC1 and 1 for RDAC2.

RS = Midscale reset, active high.

SHDN

SD = Shutdown in active high. Same as

except inverse logic.

O₁, O₂= Output logic pin latched values

D7, D6, D5, D4, D3, D2, D1, D0 = data bits.

SCL

AD1 AD0

R/W

A/B RS SD

D7 D6 D5 D4 D3 D2 D1 D0

SDA

ACK BY

AD5241

ACK BY

AD5241

ACK BY

AD5241

STOP BY

MASTER

START BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

Figure 4. Writing to the RDAC Serial Register

SCL

AD1 AD0

R/W

D7 D6 D5 D4 D3 D2 D1 D0

NO ACK BY

SDA

ACK BY

AD5241

MASTER

STOP BY

MASTER

START BY

MASTER

FRAME 2

FRAME 1

SLAVE ADDRESS BYTE

DATA BYTE FROM PREVIOUSLY SELECTED

RDAC REGISTER IN WRITE MODE

Figure 5. Reading Data from a Previously Selected RDAC Register in Write Mode

Rev. C | Page ꢁ of 20

1 2 3 456 7 8...20

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