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AD5220BRMZ10 PDF预览

AD5220BRMZ10

更新时间: 2024-01-22 17:21:09
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管转换器电阻器
页数 文件大小 规格书
12页 1394K
描述
10K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 128 POSITIONS, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8

AD5220BRMZ10 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP8,.19针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.63
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:154413Samacsys Pin Count:8
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:AD5220BRMZ10Samacsys Released Date:2015-04-16 09:48:08
Is Samacsys:N其他特性:ALSO OPERATES AT 5V SUPPLY
标称带宽:0.65 kHz控制接口:INCREMENT/DECREMENT
转换器类型:DIGITAL POTENTIOMETERJESD-30 代码:S-PDSO-G8
JESD-609代码:e3长度:3 mm
湿度敏感等级:1功能数量:1
位置数:128端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.19封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3/5 V认证状态:Not Qualified
电阻定律:LINEAR最大电阻容差:30%
最大电阻器端电压:5.5 V最小电阻器端电压:
座面最大高度:1.1 mm子类别:Digital Potentiometers
标称供电电压:3 V表面贴装:YES
技术:CMOS标称温度系数:800 ppm/ °C
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
标称总电阻:10000 Ω宽度:3 mm
Base Number Matches:1

AD5220BRMZ10 数据手册

 浏览型号AD5220BRMZ10的Datasheet PDF文件第6页浏览型号AD5220BRMZ10的Datasheet PDF文件第7页浏览型号AD5220BRMZ10的Datasheet PDF文件第8页浏览型号AD5220BRMZ10的Datasheet PDF文件第10页浏览型号AD5220BRMZ10的Datasheet PDF文件第11页浏览型号AD5220BRMZ10的Datasheet PDF文件第12页 
AD5220  
OPERATION  
Ax  
R
R
The AD5220 provides a 128-position digitally controlled vari-  
able resistor (VR) device. Changing the VR settings is accom-  
plished by pulsing the CLK pin while CS is active low. The  
direction of the increment is controlled by the U/D (UP/DOWN)  
control input pin. When the wiper hits the end of the resistor  
(Terminals A or B) additional CLK pulses no longer change  
the wiper setting. The wiper position is immediately decoded  
by the wiper decode logic changing the wiper resistance. Ap-  
propriate debounce circuitry is required when push button  
switches are used to control the count sequence and direction  
of count. The exact timing requirements are shown in Figure 3.  
The AD5220 powers ON in a centered wiper position exhibit-  
S
D0  
D1  
D2  
D3  
D4  
D5  
D6  
S
Wx  
RDAC  
UP/DOWN  
CNTR  
&
DECODE  
R
R
S
Bx  
ing nearly equal resistances of RWA and RWB  
.
= R  
/128  
S
NOMINAL  
Figure 38. AD5220 Equivalent RDAC Circuit  
V
DD  
CLK  
D
A
EN  
PROGRAMMING THE VARIABLE RESISTOR  
CS  
E
C
O
D
E
UP/  
DOWN  
CNTR  
7
W
Rheostat Operation  
The nominal resistance of the RDAC between terminals A and  
B is available with values of 10 k, 50 k, and 100 k. The  
final three characters of the part number determine the nominal  
resistance value, e.g., 10 k=10; 50 k= 50; 100 k= 100.  
The nominal resistance (RAB) of the VR has 128 contact points  
accessed by the wiper terminal, plus the B terminal contact. At  
power ON the resistance from the wiper to either end Terminal  
A or B is approximately equal. Clocking the CLK pin will in-  
crease the resistance from the Wiper W to Terminal B by one  
unit of RS resistance (see Figure 38). The resistance RWB is  
determined by the number of pulses applied to the clock pin.  
Each segment of the internal resistor string has a nominal resis-  
tance value of RS = RAB/128, which becomes 78 in the case of  
the 10 kAD5220BN10 product. Care should be taken to limit  
the current flow between W and B in the direct contact state to  
a maximum value of 5 mA to avoid degradation or possible de-  
struction of the internal switch contact.  
B
U/D  
RS  
GND  
POR  
40  
H
AD5220  
Figure 35. Block Diagram  
DIGITAL INTERFACING OPERATION  
The AD5220 contains a three-wire serial input interface. The  
three inputs are clock (CLK), CS and UP/DOWN (U/D). The  
negative-edge sensitive CLK input requires clean transitions to  
avoid clocking multiple pulses into the internal UP/DOWN  
counter register, see Figure 35. Standard logic families work  
well. If mechanical switches are used for product evaluation  
they should be debounced by a flip-flop or other suitable  
means. When CS is taken active low the clock begins to incre-  
ment or decrement the internal UP/DOWN counter dependent  
upon the state of the U/D control pin. The UP/DOWN counter  
value (D) starts at 40H at system power ON. Each new CLK  
pulse will increment the value of the internal counter by one  
LSB until the full scale value of 3FH is reached as long as the  
U/D pin is logic high. If the U/D pin is taken to logic low the  
counter will count down stopping at code 00H (zero-scale).  
Additional clock pulses on the CLK pin are ignored when the  
wiper is at either the 00H position or the 3FH position.  
Like the mechanical potentiometer the RDAC replaces, it is  
totally symmetrical (see Figure 38). The resistance between the  
Wiper W and Terminal A also produces a digitally controlled  
resistance RWA. When these terminals are used the B–terminal  
should be tied to the wiper.  
The typical part-to-part distribution of RBA is process lot depen-  
dent having a ±30% variation. The change in RBA with tempera-  
ture has a 800 ppm/°C temperature coefficient.  
All digital inputs (CS, U/D, CLK) are protected with a series  
input resistor and parallel Zener ESD structure shown in  
Figure 36.  
The RBA temperature coefficient increases as the wiper is pro-  
grammed near the B-terminal due to the larger percentage con-  
tribution of the wiper contact switch resistance, which has a  
0.5%/°C temperature coefficient. Figure 14 shows the effect of  
the wiper contact resistance as a function of code setting. An-  
other performance factor influenced by the switch contact resis-  
tance is the relative linearity error performance between the  
10 k, and the 50 kor 100 kversions. The same switch  
contact resistance is used in all three versions. Thus the perfor-  
mance of the 50 kand 100 kdevices which have the least  
impact on wiper switch resistance exhibits the best linearity  
error, see Figures 7 and 8.  
1k⍀  
LOGIC  
Figure 36. Equivalent ESD Protection Digital Pins  
20⍀  
A, B, W  
GND  
Figure 37. Equivalent ESD Protection Analog Pins  
–8–  
REV.  
A

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