AD5220–SPECIFICATIONS
(VDD = +3 V ؎ 10% or +5 V ؎ 10%, VA = +VDD, VB = 0 V, –40؇C < TA < +85؇C unless
otherwise noted)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL2
R-DNL
RWB, VA = NC, RAB = 10 kΩ
RWB, VA = NC, RAB = 50 kΩ or 100 kΩ
RWB, VA = NC, RAB = 10 kΩ
RWB, VA = NC, RAB = 50 kΩ or 100 kΩ
TA = +25°C
–1
–0.5
–1
–0.5
–30
±0.4
±0.1
±0.5
±0.1
+1
+0.5
+1
+0.5
+30
LSB
LSB
LSB
LSB
%
Resistor Nonlinearity2
R-INL
Nominal Resistor Tolerance
Resistance Temperature Coefficient
Wiper Resistance
∆R
∆RAB/∆T
RW
VAB = VDD, Wiper = No Connect
IW = VDD/R, VDD = +3 V or +5 V
800
40
ppm/°C
Ω
100
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
INL
7
–1
–0.5
–1
–0.5
Bits
Integral Nonlinearity3
RAB = 10 kΩ
RAB = 50 kΩ, 100 kΩ
RAB = 10 kΩ
RAB = 50 kΩ, 100 kΩ
Code = 40H
Code = 7FH
±0.5
±0.2
±0.4
±0.1
20
+1
+0.5
+1
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
Differential Nonlinearity Error3
DNL
+0.5
Voltage Divider Temperature Coefficient ∆VW/∆T
Full-Scale Error
Zero-Scale Error
VWFSE
VWZSE
–2
0
–0.5
+0.5
0
+1
Code = 00H
RESISTOR TERMINALS
Voltage Range4
VA, VB, VW
CA, CB
CW
0
VDD
V
Capacitance5 A, B
f = 1 MHz, Measured to GND, Code = 40H
f = 1 MHz, Measured to GND, Code = 40H
VA = VB = VW
10
48
7.5
pF
pF
nA
Capacitance5 W
Common-Mode Leakage
ICM
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
VIH
VIL
IIL
VDD = +5 V/+3 V
VDD = +5 V/+3 V
VIN = 0 V or +5 V
2.4/2.1
2.7
V
V
µA
pF
0.8/0.6
±1
Input Current
Input Capacitance5
CIL
5
POWER SUPPLIES
Power Supply Range
Supply Current
VDD
IDD
PDISS
PSS
5.5
40
200
0.015
V
µA
µW
%/%
VIH = +5 V or VIL = 0 V, VDD = +5 V
VIH = +5 V or VIL = 0 V, VDD = +5 V
15
75
0.004
Power Dissipation6
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS5, 7, 8
Bandwidth –3 dB
BW_10K
BW_50K
RAB = 10 kΩ, Code = 40H
RAB = 50 kΩ, Code = 40H
650
142
69
kHz
kHz
kHz
%
BW_100K RAB = 100 kΩ, Code = 40H
THDW
tS
Total Harmonic Distortion
VW Settling Time
VA =1 V rms + 2.5 V dc, VB = 2.5 V dc, f = 1 kHz
VA = VDD, VB = 0 V, 50% of Final Value,
10K/50K/100K
0.002
0.6/3/6
14
µs
nV/√Hz
Resistor Noise Voltage
eNWB
RWB = 5 kΩ, f = 1 kHz
INTERFACE TIMING CHARACTERISTICS Applies to All Parts5, 9
Input Clock Pulsewidth
CS to CLK Setup Time
CS Rise to Clock Hold Time
U/D to Clock Fall Setup Time
tCH, tCL
tCSS
tCSH
Clock Level High or Low
25
20
20
10
ns
ns
ns
ns
tUDS
NOTES
1Typicals represent average readings at +25°C and VDD = +5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.
3INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.
4Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5Guaranteed by design and not subject to production test.
6PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
7Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-
width. The highest R value results in the minimum overall power consumption.
8All dynamic characteristics use VDD = +5 V.
9See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both VDD = +3 V or +5 V.
Specifications subject to change without notice.
–2–
REV. 0